| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl: Add variant_mainboard_final()
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Enable LPC ComB
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Adjust GPIOs
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Disable SATA Port 0
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Enable SD-Card
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-10-11 |
Mario Scheithauer | mb/siemens/mc_ehl2: Update SPD for DDR4 devices
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-05-30 |
Mario Scheithauer | mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-05-30 |
Mario Scheithauer | mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-02-10 |
Mario Scheithauer | mb/siemens/mc_apl2: Switch I2C bus for RX6110SA
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2021-01-20 |
Mario Scheithauer | mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2020-10-05 |
Mario Scheithauer | mb/siemens/mc_apl6: Enable eMMC
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-11-07 |
Mario Scheithauer | soc/intel/{apl,dnv,quark}: Use strip_quotes for FSP...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-09-05 |
Mario Scheithauer | mb/siemens/mc_apl5: Disable IGD if no EDID data available
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-07-18 |
Mario Scheithauer | mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-07-18 |
Mario Scheithauer | mb/siemens/mc_apl1: Disable all UHS-I SD-Card speed...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-07-12 |
Mario Scheithauer | mb/siemens/mc_apl3: Enable LPSS UART 1
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-07-11 |
Mario Scheithauer | mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-07-11 |
Mario Scheithauer | mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-06-21 |
Mario Scheithauer | siemens/mc_apl5: Change PTN interface settings
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-06-21 |
Mario Scheithauer | siemens/mc_apl5: Enable TPM support
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-06-06 |
Mario Scheithauer | siemens/mc_apl5: Add own GPIO table
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-04-08 |
Mario Scheithauer | siemens/mc_apl5: Remove reduced clock rate for I2C0
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-03-08 |
Mario Scheithauer | src/soc/intel/apollolake/cpu.c: Set up local APIC
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-03-03 |
Mario Scheithauer | sb/intel/common/firmware: Don't touch descriptor region
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-02-13 |
Mario Scheithauer | siemens/mc_apl2: Remove double entry from devicetree
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-01-30 |
Mario Scheithauer | siemens/mc_apl2: Change SERIRQ mode
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-01-30 |
Mario Scheithauer | siemens/mc_apl2: Correct whitespace of devicetree
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-01-30 |
Mario Scheithauer | siemens/mc_apl2: Activate TPM support
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-01-16 |
Mario Scheithauer | siemens/mc_apl4: Change UART_FOR_CONSOLE index
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2019-01-11 |
Mario Scheithauer | siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLE
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-29 |
Mario Scheithauer | siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-29 |
Mario Scheithauer | siemens/mc_apl5: Set bus master bit for on-board PCI...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-29 |
Mario Scheithauer | siemens/mc_apl5: Enable SDCARD
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-27 |
Mario Scheithauer | siemens/mc_apl5: Adjust the settings for the PCIe root...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-26 |
Mario Scheithauer | siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-18 |
Mario Scheithauer | siemens/mc_apl5: Add new mainboard variant mc_apl5
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-16 |
Mario Scheithauer | siemens/mc_apl4: Clean up ramstage
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-16 |
Mario Scheithauer | siemens/mc_apl4: Overwrite swizzle data for LPDDR4
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl4: Enable SDCARD
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl4: Remove external RTC from I2C0
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl4: Enable all PCIe root ports
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl4: Remove reduced clock rate for I2C0
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl4: Disable CLKREQ of PCIe root ports
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl3: Set Full Reset Bit into Reset Control...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl3: Set bus master bit for on-board PCI...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl3: Remove the correction of the Tx signal...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-12 |
Mario Scheithauer | siemens/mc_apl3: Adjust Legacy IRQ routing for PCI...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl4: Add new mainboard variant mc_apl4
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl2: Adjust GPIO settings for mc_apl2
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl3: Disable I2C7 over devicetree
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl3: Enable all PCIe root ports
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl3: Remove reduced clock rate for I2C0
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl3: Disable CLKREQ of PCIe root ports
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-11-07 |
Mario Scheithauer | siemens/mc_apl3: Adjust GPIO settings for mc_apl3
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-10-30 |
Mario Scheithauer | siemens/mc_apl3: Add new mainboard variant mc_apl3
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-10-01 |
Mario Scheithauer | siemens/mc_apl1: Activate clock spreading for PTN3460
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-09-27 |
Mario Scheithauer | siemens/mc_apl1: Add new mainboard variant mc_apl2
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-09-27 |
Mario Scheithauer | siemens/mc_apl1: Make the DDR memory swizzle data configurable
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-31 |
Mario Scheithauer | siemens/mc_apl1: Correct the Tx signal from SATA interface
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-28 |
Mario Scheithauer | siemens/mc_apl1: Extend circuit life by clock gating...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-27 |
Mario Scheithauer | siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-24 |
Mario Scheithauer | siemens/mc_apl1: Select DDR50 mode for eMMC
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-24 |
Mario Scheithauer | soc/intel/apollolake: Make eMMC max speed configurable
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-23 |
Mario Scheithauer | siemens/mc_apl1: Make adjustments for the 1st redesign...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-08-23 |
Mario Scheithauer | siemens/mc_apl1: Move board specific things to mc_apl1...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-04-27 |
Mario Scheithauer | siemens/mc_apl1: Move board specific things to mc_apl1...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-04-26 |
Mario Scheithauer | siemens/mc_apl1: Provide baseboard and variant concepts
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-04-13 |
Mario Scheithauer | siemens/mc_apl1: Fix accuracy issue with IDT PMIC
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-04-11 |
Mario Scheithauer | siemens/mc_apl1: Make DRAM configuration more flexible
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2018-04-11 |
Mario Scheithauer | soc/intel/common/block/cpu: Fix cpu_get_power_max
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-21 |
Mario Scheithauer | arch/x86: Write ACPI DBG2 table only if the device...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-07 |
Mario Scheithauer | siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-07 |
Mario Scheithauer | src: Fix all Siemens copyrights
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-03 |
Mario Scheithauer | soc/intel/apollolake: Add APL CPU device ID
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-03 |
Mario Scheithauer | siemens/mc_apl1: Enable I2C0 with 100kHz
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-03 |
Mario Scheithauer | siemens/mc_apl1: Set coreboot ready LED
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-03 |
Mario Scheithauer | siemens/mc_apl1: Add legacy IRQ routing for PCI devices
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-11-03 |
Mario Scheithauer | soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-09-28 |
Mario Scheithauer | siemens/nc_fpga: Move some parameters to another function
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-09-21 |
Mario Scheithauer | siemens/mc_apl1: Move SCI to IRQ 10
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-09-21 |
Mario Scheithauer | soc/intel/apollolake: Make SCI configurable
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-09-08 |
Mario Scheithauer | siemens/mc_apl1: Disable internal UARTs
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-09-08 |
Mario Scheithauer | siemens/mc_apl1: Set bus master bit for on-board PCI...
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-07-27 |
Mario Scheithauer | siemens/mc_apl1: Select skip RAPL configuration
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-07-27 |
Mario Scheithauer | soc/intel/apollolake: Make usage of RAPL selectable
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-07-20 |
Mario Scheithauer | siemens/mc_apl1: Activate ECC for DRAM
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-07-20 |
Mario Scheithauer | siemens/mc_apl1: Include platform.asl
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-07-20 |
Mario Scheithauer | soc/intel/apollolake: Implement _PIC method into ACPI
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-07-18 |
Mario Scheithauer | siemens/mc_apl1: Disable SDCARD
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-06-23 |
Mario Scheithauer | siemens/mc_apl1: Enable decoding for COM 3 on LPC
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-06-23 |
Mario Scheithauer | siemens/mc_apl1: Disable XDCI
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-06-13 |
Mario Scheithauer | siemens/mc_apl1: Enable decoding for COM 3 on LPC
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-06-13 |
Mario Scheithauer | siemens/mc_apl1: Use Siemens NC FPGA driver
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-06-13 |
Mario Scheithauer | siemens/nc_fpga: Expand FPGA functionality
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-06-13 |
Mario Scheithauer | vendorcode/siemens: Add new values to hwilib
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-05-17 |
Mario Scheithauer | siemens/mc_apl1: Program eMMC DLL settings
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
| 2017-05-17 |
Mario Scheithauer | siemens/mc_apl1: Select external 8250 UART
...off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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commit | commitdiff | tree |
