| commit | 6c52c0b2ac7903928f16fa125009a2f1b88b5728 | |
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | |
| Tue, 13 Nov 2018 10:05:30 +0000 (13 11:05 +0100) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Fri, 16 Nov 2018 07:33:46 +0000 (16 07:33 +0000) | ||
| tree | fb07c5328ebcbded3e2c876a56de19d701acdc08 | treesnapshot (tar.gz zip) |
| parent | bd3568aea10eaf353ae225f073faf31a29516b88 | commitdiff |
siemens/mc_apl4: Overwrite swizzle data for LPDDR4
This mainboard is equipped with LPDDR4 modules. The corresponding memory
swizzle data must be set for this purpose.
Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard is equipped with LPDDR4 modules. The corresponding memory
swizzle data must be set for this purpose.
Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc | diffblobblamehistory | |
| src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c | [new file with mode: 0644] | blob |