mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs
commit92e4ed170232dd6e460be996772f07a26e620677
authorMario Scheithauer <mario.scheithauer@siemens.com>
Thu, 14 Jan 2021 13:54:38 +0000 (14 14:54 +0100)
committerPatrick Georgi <pgeorgi@google.com>
Wed, 20 Jan 2021 12:26:42 +0000 (20 12:26 +0000)
treed3ae07243c2130e250dfa4594e6b08f5c5ee533e
parent1bc061ee90bf87b89c93913b9116ad5a842e8b6a
mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDs

Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.

The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs

TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'

Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
src/mainboard/siemens/mc_apl1/mainboard.c
src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb