| commit | 4946804f0b6536df3e7a46654c0dbbc3172b1de8 | |
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | |
| Thu, 8 Nov 2018 12:49:24 +0000 (8 13:49 +0100) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Mon, 12 Nov 2018 07:26:13 +0000 (12 07:26 +0000) | ||
| tree | 291330d78456374b1799d9e4713a413469aee2a3 | treesnapshot (tar.gz zip) |
| parent | 04ea73ee78bceb680a2565777c4c7774c2ad1a8e | commitdiff |
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c | diffblobblamehistory |