| commit | 05a2b1aacdc9f8c47d6e0f857a0429b54816ca48 | |
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | |
| Tue, 18 Jul 2017 13:19:18 +0000 (18 15:19 +0200) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Thu, 20 Jul 2017 04:44:58 +0000 (20 04:44 +0000) | ||
| tree | 8aa4a32125dadf045ed020fa86629bf7022d3f19 | treesnapshot (tar.gz zip) |
| parent | d27a565211a7bbd647599efe69695686de142e51 | commitdiff |
siemens/mc_apl1: Activate ECC for DRAM
This mainboard is equipped with DDR3L modules which support ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.
Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard is equipped with DDR3L modules which support ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.
Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| src/mainboard/siemens/mc_apl1/romstage.c | diffblobblamehistory |