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riscv: sifive_u: Update PLIC hart topology configuration string
2019-09-17
Bin Meng
ris
c
v: sifive_u: Up
d
ate P
L
IC hart topolog
y
configuration
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
s
ifi
v
e
_
u: Update hart co
n
figuration to reflect
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
Meng
riscv:
sifive_u: Set
the minimum numb
e
r of cpus to 2
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: h
a
rt: Add a "hart
i
d-base" pro
p
e
r
ty to RISC-V
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: hart: Extract hart
rea
l
ize to a se
p
arate r
o
ut
i
ne
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
Add a
s
ifive_cpu
.
h to includ
e
both E and U
cpu
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: sif
i
ve_e: D
r
op s
i
f
ive_mmio_emulate
(
)
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n
Meng
ris
c
v
:
sifive_e:
p
rci: U
p
d
ate
t
he PRCI register block
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Men
g
ris
c
v: sifiv
e
_e
:
prci:
Fix
a
t
y
po of hfxosccfg register
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: sifi
v
e: Rename sifive_prci
.
{
c
, h} to sif
i
ve_e_prc
i
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin
M
eng
riscv: sifive_u: R
e
move the unne
c
e
ssary incl
u
d
e of
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
iscv: roms: Rem
o
v
e
executable
a
ttribute of opensbi
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv:
h
w:
Remove the unnecessary in
c
lu
d
e of targe
t
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv:
h
w: Change to us
e
qemu_l
o
g_mask(LOG_GUE
S
T_ER
R
O
R
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv
:
hw
:
C
h
ange
c
reate
_
fdt() to retur
n
vo
i
d
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
in Meng
riscv:
hw:
R
emove no
t
needed PLIC
prop
e
rti
e
s in de
v
ice
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
riscv:
h
w:
Use qemu_fdt
_
set
p
r
o
p_cell() for property
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv: hw: Remove s
u
p
erfluous "li
n
ux, ph
a
nd
l
e" pr
o
perty
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Meng
r
i
scv: hw: Remove
duplicated "
h
w/hw
.
h" inclusion
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
r
i
scv: si
f
ive_t
e
s
t
: Ad
d
res
e
t f
u
nctionali
t
y
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
B
i
n Meng
risc
v
:
hmp: Add a comman
d
to
s
h
o
w virtual memory
ma
p
pin
g
s
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Me
n
g
riscv: Reso
l
ve
f
ull pa
t
h
o
f the given bio
s
i
mag
e
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bi
n
Men
g
r
i
scv: Add a helper r
o
utine fo
r
f
i
n
ding f
i
rmware
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Bin Meng
riscv: rv32
:
Root pag
e
table address can be
l
arge
r
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
A
l
istai
r
Francis
targ
e
t/riscv: Update the Hyp
e
rvisor CSRs
to v0
.
4
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Ali
s
tai
r
Francis
target/riscv: Create function to test if F
P
i
s
e
n
a
bled
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Francis
riscv:
p
l
i
c: Remov
e
unused
i
nt
e
rrupt funct
i
ons
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Philippe Mathieu
.
.
.
tar
g
et/
r
i
s
cv/pmp: Convert qemu_log_
m
ask(
L
OG_TRACE)
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Philippe M
a
thieu
.
.
.
target/riscv/pmp:
R
estrict p
r
iviled
g
ed
P
M
P
to
s
ystem
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Guenter R
o
eck
r
iscv:
sifive_u:
F
ix clock
-
names proper
t
y for ethernet
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
Gue
n
t
er Roeck
riscv: sivive_u: A
d
d dummy seria
l
clock and
aliases
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-09-17
G
uenter Roeck
riscv: s
i
f
i
ve_u:
Add su
p
port for loading
i
n
itr
d
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-07-26
A
l
i
s
ta
i
r Francis
riscv/boot: Fix
u
p
t
h
e
RISC-V firmware warning
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-07-18
A
l
ista
i
r
F
rancis
hw/riscv: Load Op
e
nSBI as the
d
efault firmware
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-07-18
Alis
t
air Fr
a
ncis
roms: Add OpenSBI vers
i
on 0
.
4
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Alistair Fr
a
ncis
hw/riscv
:
Ext
e
nd the kernel loading support
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Ali
s
t
air
Francis
hw/riscv: Add support f
o
r loading a firmware
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Ali
s
t
air
Franci
s
h
w
/ris
c
v: Split out the boot
functions
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
B
i
n Me
n
g
riscv: s
i
f
ive_u: Update t
h
e
plic hart config t
o
support
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
B
in Men
g
ris
c
v
: sifive_u
:
Do not create hard-co
d
ed phand
l
e
s
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Wladimi
r
J
.
van
.
.
.
disas/riscv: Fix `rdinstreth`
c
ons
t
raint
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-27
Michael Clark
d
is
a
s/riscv: Disas
s
emble
r
e
serve
d
comp
r
essed enco
d
ings
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Atish Pat
r
a
riscv: vi
r
t: Add cpu-t
o
pology DT
node
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Jim Wilson
R
ISC-V: Update s
y
scal
l
list for 32-bit supp
o
rt
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Joel Sing
RI
S
C-V: Clear load reservati
o
ns on context switch a
n
d
S
C
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
Palmer Dabb
e
lt
RISC-V:
A
dd
s
upport for the Zicsr extension
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-26
P
a
lmer Dabbelt
RISC-V: Add
s
upport for the Z
i
fencei
e
xte
n
sion
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Francis
t
a
rget/riscv: Add support
f
o
r
d
isabling
/
enab
l
ing Cou
n
ters
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Fr
a
ncis
targ
e
t/riscv: Remove
u
se
r
version
informati
o
n
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alis
t
air Franci
s
targ
e
t/riscv:
R
eq
u
ire either I or
E
base ext
e
n
s
ion
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
A
l
istair Francis
qemu-deprecated
.
t
e
xi: Depre
c
ate the RISC-V privle
d
ge
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
A
l
istair
F
ra
n
cis
target/riscv:
Set pr
i
vledge
spec 1
.
11
.
0 as def
a
ult
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-25
Alista
i
r
F
rancis
target/
r
is
c
v: Add the mcountinhibit CSR
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Ali
s
tair Francis
target/r
i
scv: Add the pri
v
ledge spec
v
ers
i
on 1
.
1
1
.
0
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Alistair Franc
i
s
target/riscv: Restructu
r
e deprecat
d
C
PUs
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
P
alme
r
D
abbelt
RISC-V: Fix
a
memory le
a
k whe
n
realiz
i
ng a sifive_e
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
B
i
n Me
n
g
risc
v
: virt:
C
orrect
p
ci "bus-range" en
c
o
d
ing
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
H
e
s
h
a
m
Almatary
RISC
-
V: Fix a
P
MP check with the correct
a
ccess size
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
H
esham
A
lmatary
RISC-V: Fix a PMP bu
g
where it su
c
c
eeds e
v
en i
f
PMP
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hes
h
am Almatary
R
ISC-V
:
Check PMP during Page T
a
ble W
a
l
k
s
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hesham
A
lmatary
R
I
SC-V: Check for the
e
ffective memory privilege mode
.
.
.
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
He
s
h
a
m Almatary
RISC
-
V
:
Raise ac
c
ess
faul
t
exceptions on
P
MP vi
o
lati
o
ns
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Hes
h
am Almat
a
ry
RISC-V: O
n
ly Check P
M
P if
MM
U
translation succeeds
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Mi
c
hael Cla
r
k
targ
e
t/r
i
scv:
Imp
l
ement ris
c
v_cpu_
u
nassigned_access
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
D
a
yeol Le
e
t
a
rget/riscv: Fi
x
PMP r
a
nge boundary
address b
u
g
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Natha
n
iel Graff
sif
i
v
e
_prci: Read and write P
R
CI reg
i
st
e
rs
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-06-24
Al
i
stair Francis
target/riscv: Allow
s
etting ISA extensions via CPU
.
.
.
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-05-24
Jonath
a
n
B
ehrens
target/risc
v
:
O
nly flush TLB if
S
ATP
.
A
S
ID change
s
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-05-24
Jon
a
than Behrens
target/riscv: More
ac
c
urate ha
n
dling of `sip
`
C
S
R
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-05-24
Richard Henderson
target/riscv: Add checks for se
v
eral
R
VC reserved operands
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-05-24
Alistair Fra
n
ci
s
t
arget/riscv: Add the H
G
A
TP registe
r
masks
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
|
commitdiff
|
tree
2019-05-24
Ali
s
tair Francis
tar
g
et/ri
s
cv: Add the HSTATUS register
m
a
sks
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2019-05-24
Alistair Fra
n
cis
tar
g
et/r
i
s
cv:
A
dd H
y
perviso
r
CSR macr
o
s
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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2019-05-24
Alistair Francis
ta
r
get/riscv: Allow settin
g
mstatus v
i
rtulisat
i
on bits
Revieweb-by: Palmer Dabbelt <
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>
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2019-05-24
Alist
a
ir Franci
s
target/riscv:
A
d
d the M
P
V
and MTL mstatu
s
bits
Reviewed-by: Palmer Dabbelt <
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>
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>
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2019-05-24
Alistair Francis
target/riscv: Impr
o
v
e
t
h
e
sc
a
use log
i
c
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>
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>
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2019-05-24
A
listair F
r
ancis
target/riscv:
T
rigger interrupt on M
I
P
upd
a
te asynchronousl
y
Reviewed-by: Palmer Dabbelt <
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2019-05-24
Al
i
s
t
a
i
r Francis
target
/
riscv: M
a
r
k
p
rivilege level 2
as reser
v
ed
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Alistair Fr
a
n
ci
s
r
iscv: sp
i
ke: Add
a gene
r
ic
s
pike machin
e
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Alistair Francis
target/riscv: De
p
recate
t
he generic no MMU
C
P
Us
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Alistair Francis
t
arg
e
t/r
i
sc
v
: Add a ba
s
e
32 and 64
b
it CPU
Reviewed-by: Palmer Dabbelt <
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>
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>
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2019-05-24
Alistair Francis
target/riscv: Create
s
e
ttab
l
e
CPU properties
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Alistair Fr
a
n
c
i
s
riscv:
virt: A
l
low s
p
ecifying a CPU
via commandline
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>
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2019-05-24
Ali
s
tair Francis
linux
-
user/ri
s
cv: Add the CP
U
type as a comme
n
t
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>
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2019-05-24
Jonatha
n
B
ehr
e
ns
target/riscv: Remove unused include o
f
riscv_htif
.
h
.
.
.
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Richa
r
d He
n
d
e
r
s
on
ta
r
g
e
t/riscv: Remove spaces
f
rom registe
r
names
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Richard
H
enderson
target/riscv: Sp
l
i
t
gen_arith_im
m
into
f
unc
t
i
onal and
.
.
.
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
R
i
c
har
d
Henderson
target/
r
iscv
:
Spli
t
RVC32 and RVC64 insns into s
e
parate
.
.
.
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Richa
r
d
Henderson
target/
r
iscv: Use pattern
g
roups in insn1
6
.
decode
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
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>
commit
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2019-05-24
Richard
H
en
d
erson
target/riscv: Merge argument decode fo
r
R
V
C shif
t
i
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Richard H
e
nderson
target/riscv: Merg
e
argument
s
ets
for
insn32 and i
n
sn16
Reviewed-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Ric
h
ard Hend
e
r
s
on
target/ri
s
c
v
: Use --static
-
d
e
code fo
r
d
e
codetree
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Ri
c
hard
H
enderson
target/ri
s
cv: Name the argument
set
s
f
or all of
i
nsn32
.
.
.
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-05-24
Fabi
e
n Ch
o
utea
u
RI
S
C-V: fix single ste
p
ping over ret and
o
ther bra
n
c
h
ing
.
.
.
Signed-off-by: Palmer Dabbelt <
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>
commit
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2019-05-24
Jo
n
athan Be
h
rens
target/r
i
sc
v
:
Do not all
o
w
sfence
.
vma from user
mod
e
Signed-off-by: Palmer Dabbelt <
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>
commit
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2019-05-24
Fa
b
i
e
n Chouteau
Si
F
ive RISC-V
G
P
I
O De
v
ice
Reviewed-by: Palmer Dabbelt <
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>
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>
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2019-04-04
Alistair Francis
riscv: p
l
ic:
L
og guest er
r
o
rs
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
commit
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2019-04-04
Ali
s
tair Francis
riscv: plic: Fix
i
ncorrect
irq
c
alculation
Signed-off-by: Palmer Dabbelt <
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>
commit
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2019-03-26
Kito Cheng
t
a
rget/
r
iscv: Fix wrong expanding for c
.
f
swsp
Reviewed-by: Palmer Dabbelt <
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>
Signed-off-by: Palmer Dabbelt <
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>
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2019-03-22
Palm
e
r Dabbelt
target/riscv: Zero extend the inp
u
ts of divuw and
r
emuw
Signed-off-by: Palmer Dabbelt <
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>
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