2021-03-23 | Bin Meng | docs/system: riscv: Add documentation for 'microchip... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Bin Meng | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Bin Meng | hw/block: m25p80: Support fast read for SST flashes Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Add proper two-stage lookup exception... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Fix read and write accesses to vsip and... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Asherah Connor | hw/riscv: allow ramfb on virt Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Asherah Connor | hw/riscv: Add fw_cfg support to virt Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Use background registers also for MSTATUS_MPV Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Make VSTIP and VSEIP read-only in hip Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Georg Kotheimer | target/riscv: Adjust privilege level for HLV(X)/HSV... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Jim Shu | target/riscv: flush TLB pages if PMP permission has... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Jim Shu | target/riscv: add log of PMP permission checking Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Jim Shu | target/riscv: propagate PMP permission to TLB page Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Alexander Wagner | hw/char: disable ibex uart receive if the buffer is... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-23 | Frank Chang | target/riscv: fix vs() to return proper error code Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: virt: Map high mmio for PCIe Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: virt: Limit RAM size in a 32-bit system Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: Drop 'struct MemmapEntry' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Alistair Francis | MAINTAINERS: Add a SiFive machine section Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Laurent Vivier | goldfish_rtc: re-arm the alarm after migration Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | docs/system: riscv: Add documentation for sifive_u... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | docs/system: Add RISC-V documentation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | docs/system: Sort targets in alphabetical order Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: sifive_u: Add QSPI2 controller and connect... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/riscv: sifive_u: Add QSPI0 controller and connect... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/ssi: Add SiFive SPI controller support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/block: m25p80: Add various ISSI flash information Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/block: m25p80: Add ISSI SPI flash support Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Yifei Jiang | target-riscv: support QMP dump-guest-memory Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | roms/opensbi: Upgrade from v0.8 to v0.9 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | hw/misc: sifive_u_otp: Use error_report() when block... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-03-04 | Bin Meng | target/riscv: Declare csr_ops[] with a known size Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Alistair Francis | riscv: Pass RISCVHartArrayState by pointer Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Remove built-in GDB XML files for CSRs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Generate the GDB XML file for CSR registers... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Add CSR name in the CSR function table Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | target/riscv: Make csr_ops[CSR_TABLE_SIZE] external Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Green Wan | hw/misc/sifive_u_otp: handling the fails of blk_pread... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Atish Patra | target/riscv/pmp: Raise exception if no PMP entry is... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Atish Patra | RISC-V: Place DTB at 3GB boundary instead of 4GB Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Sylvain Pelissier | gdb: riscv: Add target description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Xuzhou Cheng | hw/block: m25p80: Implement AAI-WP command support... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2021-01-16 | Bin Meng | hw/block: m25p80: Don't write to flash if write is... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | riscv/opentitan: Update the OpenTitan memory layout Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | hw/riscv: Use the CPU to determine if 32-bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: cpu: Set XLEN independently from target Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: csr: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: cpu_helper: Remove compile time XLEN... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: cpu: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: Specify the XLEN for CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: Add a riscv_cpu_is_32bit() helper function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: fpu_helper: Match function defs in HELPER... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | hw/riscv: sifive_u: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | hw/riscv: spike: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | hw/riscv: virt: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | hw/riscv: boot: Remove compile time XLEN checks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | riscv: virt: Remove target macro conditionals Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | riscv: spike: Remove target macro conditionals Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | hw/riscv: Expand the is 32-bit check to support more... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alistair Francis | intc/ibex_plic: Clear interrupts that occur during... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Alex Richardson | target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Yifei Jiang | target/riscv: Fix the bug of HLVX/HLV/HSV Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Xinhao Zhang | hw/core/register.c: Don't use '#' flag of printf format Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Vitaly Wool | hw/riscv: microchip_pfsoc: add QSPI NOR flash Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-12-18 | Anup Patel | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-14 | Alistair Francis | intc/ibex_plic: Ensure we don't loose interrupts Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-14 | Alistair Francis | intc/ibex_plic: Fix some typos in the comments Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-09 | Alistair Francis | hw/intc/ibex_plic: Clear the claim register when read Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-09 | Alistair Francis | target/riscv: Split the Hypervisor execute load helpers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-09 | Alistair Francis | target/riscv: Remove the hyp load and store functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-09 | Alistair Francis | target/riscv: Remove the HS_TWO_STAGE flag Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-09 | Alistair Francis | target/riscv: Set the virtualised MMU mode when doing... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-09 | Alistair Francis | target/riscv: Add a virtualised MMU Mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Xinhao Zhang | target/riscv/csr.c : add space before the open parenthesis '(' Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Hook the I2C1 controller Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Correct DDR memory map Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Map the reserved memory... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect the SYSREG module Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC SYSREG module... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect the IOSCB module Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC IOSCB module support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Connect DDR memory controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/misc: Add Microchip PolarFire SoC DDR Memory Controller... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Bin Meng | hw/riscv: microchip_pfsoc: Document where to look at... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add sifive_plic vmstate Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add V extension state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add H extension state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add PMP state description Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Add basic vmstate description of CPU Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Yifei Jiang | target/riscv: Merge m/vsstatus and m/vsstatush into... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Anup Patel | hw/riscv: virt: Allow passing custom DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-11-03 | Anup Patel | hw/riscv: sifive_u: Allow passing custom DTB Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Green Wan | hw/misc/sifive_u_otp: Add backend drive support Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Green Wan | hw/misc/sifive_u_otp: Add write function and write... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Yifei Jiang | target/riscv: raise exception to HS-mode at get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2020-10-22 | Alistair Francis | hw/riscv: Load the kernel after the firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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