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docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
2021-03-04
Alistair Francis
MAINTAINER
S
: Add a SiFiv
e
m
achine section
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair Fra
n
cis
linux-
u
s
e
r/sig
n
al: Decode
w
aitid si_co
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Alistai
r
F
r
a
ncis
risc
v
: P
a
s
s
RISCVHart
A
rrayStat
e
by poi
n
t
e
r
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
s
t
a
ir Francis
riscv/op
e
ntitan: Update the OpenTitan memo
r
y l
a
yout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/riscv: Us
e
t
he CPU to determin
e
if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Francis
ta
r
get/riscv: cpu: Set X
L
EN independ
e
ntly fr
o
m target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Francis
target/riscv: csr:
R
emo
v
e
c
ompile
t
ime XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
ancis
target/riscv: cpu_helpe
r
:
Rem
o
ve compile ti
m
e X
L
EN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
ta
r
ge
t
/ri
s
c
v
:
c
pu: Remove comp
i
l
e
time XLEN c
h
ecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair
Franci
s
target/riscv: Specify the X
L
E
N
for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
t
a
rget/riscv: Add a riscv_cpu_is_32
b
it() helper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Francis
tar
g
et/riscv: fpu_help
e
r:
M
atch func
t
io
n
defs in HELPE
R
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/r
i
scv: sifive_u
:
R
e
move compile
t
ime XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Fra
n
cis
hw/riscv: sp
i
ke: Remove compile t
i
me XLE
N
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/risc
v
: virt: Remov
e
c
o
mpi
l
e time X
L
EN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/riscv: boot: Remo
v
e
compile t
i
me XL
E
N checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Francis
riscv: virt
:
Remove
t
a
rg
e
t macro cond
i
tionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
a
ir Fr
a
n
cis
r
isc
v
: spike: R
e
move
t
arget
macro c
o
n
d
itionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair
Francis
target/riscv: Ad
d
a TYP
E
_R
I
SCV_C
P
U_BASE
CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Franc
i
s
h
w/riscv: Expand th
e
is 32-bit check
t
o su
p
port mor
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
int
c
/ibex_
p
l
i
c: Cle
a
r interrupts that occu
r
during
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
A
l
istair
F
ranc
i
s
reg
i
st
e
r: Remove unnecessary NULL
c
heck
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alist
a
ir Franci
s
intc/
i
b
e
x_plic: Ensur
e
we don't loose
i
n
t
errupts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Ali
s
tair Francis
intc/
i
bex_plic: Fix so
m
e typos in th
e
comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Ali
s
tair F
r
anci
s
hw/intc
/
i
bex
_
p
lic: Clear the
c
l
aim register whe
n
read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alista
i
r Francis
ta
r
get/riscv: Split the Hype
r
visor
e
xecute load helpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
listair Fr
a
ncis
target/riscv: Remove the hyp load
a
nd
store
fun
c
tions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
target/r
i
s
cv: Remove the HS_TWO_STA
G
E flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Fra
n
cis
t
a
rget/ri
s
cv: Set the virtuali
s
ed
M
MU mode when doin
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Ali
s
tair
F
r
a
ncis
target/ri
s
cv
:
Add a
virtua
l
ised
M
M
U M
o
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
A
listair Francis
lin
u
x
-
user/sys
c
a
ll: Fix missing t
a
r
g
e
t
_
to_host_ti
m
espec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
hw/riscv: Lo
a
d the ke
r
nel after th
e
firmw
a
re
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Franci
s
hw
/
riscv:
A
dd a ris
c
v_is_
3
2_bi
t
()
f
u
n
ction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
ta
i
r
F
rancis
h
w
/
r
i
scv: Return
the end add
r
ess of t
h
e l
o
aded firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair
F
rancis
hw/riscv: sifive_u: Allow specifyi
n
g
t
h
e C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alis
t
air Franci
s
riscv: Convert int
e
rrupt logs to use qemu_
l
og_mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
l
istair
Francis
core/regis
t
e
r: Specify
instance_s
i
ze in the TypeInfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
ta
r
g
et/riscv
:
Support
the Virtual Instruction fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
target
/
riscv: Return the exception f
r
om invalid CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/risc
v
:
Su
p
p
ort the
v0
.
6 Hy
p
ervis
o
r ex
t
ensio
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
rancis
tar
g
et/riscv: Only support little endian
g
uests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair Franci
s
tar
g
et/riscv: Only support
a
single
VSXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair
F
ra
n
ci
s
t
arget/riscv:
U
pdate
t
he
CS
R
s
to the v0
.
6 Hyp
extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv
:
U
p
date th
e
Hy
p
ervisor tra
p
return/ent
r
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
rancis
target/riscv: Fix the
interrupt cause
c
ode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistai
r
Franc
i
s
targe
t
/risc
v
: Convert MSTATUS MTL
t
o
GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair F
r
ancis
target/riscv: Don't allow gu
e
st to wr
i
te to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
rancis
target/riscv: D
o
two-s
t
ag
e
l
o
oku
p
s on hlv/hlvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stai
r
Franci
s
target/riscv:
A
llow generat
i
n
g hlv/hl
v
x/hsv instr
u
cti
o
ns
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
is
t
ai
r
Francis
target/riscv: A
l
low set
t
ing a two-stage lookup in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alista
i
r Fran
c
is
h
w
/
i
ntc
:
ibex_plic: H
o
nour source priorities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/int
c
: ibex_
p
li
c
: Don't
allow repeat interr
u
pts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
li
s
tair Franci
s
hw/intc: ibex_plic: Update the pending irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alist
a
ir Francis
hw/sd/pl1
8
1
: Replace fprint
f
(stderr, "*\n") with error_re
p
ort
(
)
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair
Franc
i
s
hw/cha
r
: Convert the I
b
ex UART to use t
h
e registerfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair F
r
anci
s
hw/char:
C
onvert the Ibex
U
A
R
T to use th
e
q
dev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair Fran
c
is
hw
/
riscv:
Allow 64 bi
t
acces
s
to
S
iFiv
e
CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fran
c
is
target/ris
c
v: Use a
smaller
g
uess
s
i
ze for no-MMU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
r
a
ncis
r
i
s
cv/opentitan: Connect the UAR
T
device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
riscv/
o
pentitan: Connect the PLIC
d
evice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
h
w/i
n
tc: Initial commit of lowR
I
SC
I
b
ex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Fra
n
cis
hw/ch
a
r: Initial
commit of Ibex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
ris
c
v/o
p
entitan:
F
ix the ROM siz
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair Francis
target/ri
s
cv
:
I
m
p
l
e
m
en
t
chec
k
s fo
r
hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair F
r
ancis
targ
e
t/riscv: Move the hfence instructio
n
s to the
r
vh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
i
r
F
r
a
nci
s
target
/
riscv: Report e
r
rors validating 2nd-s
t
age PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair Francis
tar
g
et/riscv: Set
a
cc
e
ss a
s
data_
l
oad w
h
en
val
i
d
a
ting
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistai
r
Francis
sifive_e: Suppo
r
t the rev
B
m
achine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair Francis
riscv: Initial commit
o
f Op
e
nTitan m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
t
a
rget/riscv: Add
t
he lowRIS
C
Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
t
a
rget/riscv:
D
on't set PMP
f
eatur
e
in the cpu
i
n
i
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Francis
target/riscv: Disable the MMU
c
orrectly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istai
r
Francis
target/riscv: D
o
n
'
t
overwrite the res
e
t vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
riscv/bo
o
t
:
Add a missing he
a
der
i
nc
l
ud
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stai
r
Fra
n
cis
riscv: sifive_e: M
a
nually
d
efin
e
the
m
a
chin
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistai
r
Francis
doc
s
: dep
r
ecated: Update the -bios documen
t
ation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Al
i
stair Fr
a
ncis
tar
g
et
/
riscv:
Drop support for ISA s
p
ec
v
ersio
n
1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alist
a
ir Francis
target/riscv: Re
m
ove the
d
eprecated CPU
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Al
i
st
a
ir
F
rancis
hw/ri
s
cv: s
p
ike: Remove d
e
precated ISA specific mach
i
nes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Al
i
sta
i
r Francis
riscv:
A
ND stage-1 and stage-2 protection flags
Signed-off-by:
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<alistair.francis@wdc.com>
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2020-04-29
Alistair F
r
ancis
r
iscv: D
o
n't use sta
g
e-2 PTE look
u
p protec
t
ion
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Francis
riscv/sifive_
u
:
A
dd a serial property
to
t
he sifive_u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistai
r
Fr
a
ncis
riscv/sifive_u: Fix up file ordering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Alistair Francis
linux-u
s
er: Support
fu
t
ex_t
i
me64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alis
t
air
F
rancis
linux-user
/
r
iscv: Update the sy
s
call_nr's t
o
th
e
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistai
r
F
rancis
linux-user/syscall: Add support f
o
r c
l
ock_gettim
e
64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alista
i
r Franci
s
l
inux
-
user: Protect more sy
s
calls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-17
Alistair Franci
s
target/riscv
:
Corr
e
ctly implement TSR trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target/ri
s
cv:
A
llow enabl
i
ng the Hypervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
lis
t
air
Francis
t
a
rget/risc
v
: Ad
d
the MSTATUS_MPV
_
ISSET hel
p
er macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
t
a
ir Fr
a
ncis
ta
r
ge
t
/ris
c
v: Add support for th
e
32-bit MSTATUSH CS
R
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Al
i
s
tair Francis
targ
e
t/riscv: Set htval
a
nd mtval
2
on execptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fr
a
nc
i
s
target
/
r
iscv: Raise
t
h
e
n
e
w
execptions when 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fr
a
n
c
i
s
target/
r
is
c
v:
Implement s
e
cond
stage MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
lis
t
air Francis
target/riscv: Allow spe
c
ifyi
n
g MMU
stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
targe
t
/riscv:
Resp
e
ct MPRV and SPRV
for
floating point o
p
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
listair Francis
target/riscv: Mar
k
both s
s
tatus and msstatus_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistai
r
Francis
target
/
riscv: Disab
l
e guest
FP support based on
v
irtual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
listair Francis
tar
g
et/riscv: Only set TB flags
with FP status if enable
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
listair
F
ranc
i
s
targe
t
/
r
iscv: Remove the hret instruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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