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riscv/opentitan: Update the OpenTitan memory layout
2020-12-18
Ali
s
t
a
ir Franci
s
ri
s
cv/opent
i
ta
n
: Update the OpenTitan memory lay
o
ut
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istai
r
Francis
h
w/riscv: Us
e
the CPU to determine if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/riscv: c
p
u
: Set
XLEN indepe
n
dently from target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
targ
e
t
/
riscv: csr: Remove c
o
mpile time X
L
EN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
t
ar
g
et/risc
v
:
c
pu_helper:
R
emo
v
e compile ti
m
e
XLE
N
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lis
t
a
i
r F
r
ancis
target
/
r
i
s
c
v: cpu: Remove comp
i
le
time X
L
EN che
c
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
stair
Fra
n
ci
s
t
a
r
get/ri
s
cv: Sp
e
c
ify
t
he XLEN for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r Francis
t
a
rget/r
i
scv: Add a
r
iscv_cpu_is
_
32bit() help
e
r
f
unction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
t
a
rget/riscv: fpu_helper: Match
func
t
ion d
e
fs in
H
ELPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air
Francis
hw/riscv: sifive_u: Remove co
m
pil
e
time
XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
ancis
hw/riscv: spike: Rem
o
ve compi
l
e time XLE
N
chec
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair Francis
hw/riscv: vi
r
t: Remo
v
e compile t
i
me
X
LE
N
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Francis
hw/
r
iscv:
b
o
ot: Remove com
p
ile
t
ime XL
E
N che
c
ks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir
F
r
a
ncis
riscv: vi
r
t: Remove target macro conditi
o
nal
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Francis
riscv
:
spike: Remove ta
r
g
e
t m
a
cro c
o
n
d
i
t
ionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Francis
target/riscv: Add a TYPE_RISCV_
C
P
U
_
BASE CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
s
t
air Francis
hw/ri
s
cv: Expand the is
3
2
-bit check
t
o
support
more
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
F
rancis
intc/i
b
ex_plic: C
l
ear interrupts th
a
t occur dur
i
ng
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
Alis
t
air Franc
i
s
register: Rem
o
ve
u
n
necessar
y
NULL check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Fr
a
nc
i
s
i
n
tc/
i
bex_plic
:
Ensure we don'
t
loose in
t
errupts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistai
r
Francis
intc/ibex_
p
lic:
Fix some typos in
t
he
com
m
ents
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
F
rancis
hw/intc/ib
e
x_pli
c
: Clear
the
claim
r
egist
e
r
w
h
en read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
Fran
c
is
t
a
rget/riscv: Sp
l
i
t
the H
y
p
ervisor exec
u
te
loa
d
help
e
rs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
ta
r
get/
r
iscv: Remo
v
e the
hy
p
load and stor
e
functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Fra
n
c
is
target/riscv: Remove
the HS_T
W
O_STA
G
E flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
li
s
tair Francis
target/
r
isc
v
:
Set
t
he vi
r
tu
a
lised MMU
m
ode
w
h
en doi
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Al
i
stair Francis
target/riscv: Add a
virtualised MMU Mod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alistair Fr
a
n
cis
linux-user/syscall: F
i
x missing
t
arget_to
_
host_timespec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair F
r
ancis
hw/riscv: Loa
d
the kernel after the firm
w
a
re
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistai
r
Fra
n
c
i
s
hw/riscv
:
Add a riscv_is_32_
b
it() func
t
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
l
istair
F
rancis
hw
/
riscv: Return t
h
e end addres
s
o
f
the l
o
a
d
ed firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alist
a
ir Fr
a
ncis
hw/r
i
scv: sifive_u
:
A
llow specifyin
g
the CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
riscv: Con
v
ert interrupt l
o
gs to use qe
m
u_log_mask
(
)
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
l
i
s
tair Francis
core/register:
S
pecif
y
instance_size
i
n the TypeI
n
fo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
ist
a
ir Franc
i
s
t
a
rget
/
riscv: Support t
h
e
V
i
rtual Inst
r
u
cti
o
n f
a
ult
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fra
n
c
is
target/
r
iscv: Return th
e
e
xce
p
tion from inv
a
lid CS
R
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistai
r
Francis
tar
g
et/riscv: Sup
p
or
t
the v0
.
6 Hypervisor e
x
tension
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stair Franc
i
s
tar
g
et/riscv: Only support little end
i
an guests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair Francis
target/riscv: Only support a single VSXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
targ
e
t/riscv: Update the CSRs to the
v
0
.
6 Hy
p
extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair Fr
a
ncis
t
a
rge
t
/
risc
v
:
U
p
d
ate the
H
yp
e
rvisor t
r
ap return/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
air Fra
n
cis
target/ri
s
cv: Fix the inter
r
u
p
t
cause
c
o
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair
Francis
t
a
rget/riscv: Convert MST
A
TUS
M
T
L to GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istai
r
Franc
i
s
tar
g
et/r
i
scv:
Don't allow guest to write to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
tar
g
et
/
riscv:
Do two
-
stage
looku
p
s on hlv/hlvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fra
n
cis
target/r
i
scv: Allow ge
n
erating h
l
v/hlvx/hsv instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Francis
target/ris
c
v: Allo
w
setting a two-st
a
ge lookup
i
n the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alista
i
r Francis
h
w
/
i
ntc
:
i
b
ex_plic: H
o
nour source p
r
i
orit
i
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Fran
c
is
hw/intc
:
ibex_plic
:
D
on't allow
r
e
peat interrupts
o
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair F
r
ancis
hw/intc: ibex_plic
:
Update
the
pending ir
q
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alist
a
ir
Francis
hw/s
d
/
pl181: Repla
c
e fprintf(stderr, "*\n") with error_report(
)
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Franci
s
hw/char:
C
onvert the Ibex UART to use
t
he r
e
gisterfi
e
l
ds API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Francis
hw
/
char:
Convert th
e
Ibex UART to use the qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistai
r
Francis
hw/riscv: Al
l
ow 64
b
it access to SiFive
C
LINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistai
r
Francis
target/riscv
:
Use a
smaller guess size f
o
r no-MMU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair Franc
i
s
riscv/opentitan:
Co
n
nect the UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir Fran
c
i
s
r
iscv/o
p
entitan: Co
n
nect the P
L
IC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
ista
i
r
Franc
i
s
h
w/intc: Initial commit of low
R
ISC Ibex
P
LIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
h
w
/
c
har: Init
i
al
c
ommit of
Ibex UAR
T
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fra
n
cis
risc
v
/opentitan: Fix th
e
R
O
M size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tair
F
ranc
i
s
t
arget/riscv: Impleme
n
t check
s
for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
list
a
ir Francis
t
arget/riscv: Move the
hf
e
nce in
s
t
r
uctions to the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair F
r
a
ncis
t
ar
g
et/ris
c
v: R
e
port erro
r
s val
i
datin
g
2nd-stage PT
E
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alis
t
air Francis
target/ri
s
cv: Set access as data_load
w
h
e
n valid
a
ting
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair F
r
an
c
is
si
f
ive_e:
Suppor
t
the revB mac
h
in
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
ir Francis
riscv: Initial commit of Open
T
itan m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
Francis
target/riscv: Add
t
h
e
lowR
I
SC Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franc
i
s
ta
r
get/riscv: Don't se
t
P
MP feature i
n
the cpu init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alista
i
r Francis
targe
t
/r
i
scv: Disable th
e
MM
U
correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
i
r
Francis
target/ri
s
cv: Don't overwrite the
reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franci
s
risc
v
/b
o
ot: Add a
mis
s
ing he
a
der inclu
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Franc
i
s
riscv
:
sifive_e: Manually
d
e
f
in
e
the mac
h
ine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
s
ta
i
r Francis
d
o
cs: dep
r
eca
t
e
d: U
p
date the
-
bi
o
s documentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair Francis
target/riscv: Dr
o
p suppor
t
f
or ISA spec vers
i
o
n 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alista
i
r Francis
tar
g
et/riscv: Remove the deprecated C
P
Us
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fran
c
is
hw/riscv: spike:
Remove deprecated ISA spe
c
ific machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Fra
n
cis
ris
c
v: AN
D
stage-1 and
stage-2 protect
i
o
n
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alis
t
air F
r
anc
i
s
riscv: Don't
use stage
-
2 PTE
l
ookup protection
fla
g
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
list
a
ir Francis
riscv
/
sifive_u:
A
dd a se
r
ial
p
roperty to the sif
i
ve_u S
o
C
Signed-off-by:
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<alistair.francis@wdc.com>
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2020-04-29
A
l
istai
r
F
r
a
ncis
r
i
scv
/
sifive_u: Fix up file orde
r
ing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Alistair Fra
n
ci
s
linux
-
user: Sup
p
or
t
f
u
t
e
x
_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistair Francis
lin
u
x-user/
r
i
s
cv:
U
p
date
the sys
c
all_
n
r's to the 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
A
list
a
ir Francis
linu
x
-user/syscal
l
: Add s
u
pport for clock_getti
m
e64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Ali
s
tair Francis
linux-u
s
er:
Protect more syscalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-17
Alistair Fran
c
i
s
targ
e
t/riscv: Correct
l
y im
p
lement
TSR tr
a
p
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alis
t
ai
r
F
ra
n
ci
s
target/riscv: Allow enabling th
e
Hypervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
tair Fra
n
cis
target/riscv:
Add the MST
A
TUS_MPV_
I
SSET help
e
r m
a
c
ro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Franci
s
targe
t
/riscv:
Add support for the 32-bi
t
MSTATUSH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair F
r
ancis
targe
t
/riscv:
S
et htval an
d
mtval2 on ex
e
cptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alista
i
r Francis
t
arge
t
/riscv
:
Raise t
h
e new execptions w
h
en
2
nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alist
a
ir
F
ran
c
is
targe
t
/
risc
v
:
I
m
p
lement second s
t
age MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistai
r
Fra
n
cis
target/ri
s
cv:
A
l
low specifying MMU stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistai
r
Fran
c
is
target/risc
v
: Respect
M
PRV a
n
d
S
PRV for floa
t
ing poi
n
t
ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
tair Fra
n
cis
target/riscv
:
Mark bo
t
h
sstatus
and msstatus_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
t
a
ir Francis
target
/
riscv: Di
s
ab
l
e gue
s
t FP support
b
ased on
vi
r
t
u
al
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fran
c
is
target/riscv: Only set TB flags with FP
s
tatus if e
n
ab
l
e
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
l
istair Franc
i
s
tar
g
et
/
riscv: Remove the hret
i
n
struction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target
/
ris
c
v
: Add hfence
i
nstructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
tair F
r
ancis
t
arge
t
/riscv: Add Hyperviso
r
tr
a
p
return
s
u
p
port
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target/ris
c
v
:
Add hyp
v
ervi
s
or trap
support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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