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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
2020-12-18
Ali
s
tair Francis
riscv/op
e
ntitan: U
p
d
a
te the Op
e
n
T
ita
n
memory
lay
o
ut
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r Francis
hw/riscv
:
Use the CPU to determ
i
ne if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lis
t
ai
r
Fra
n
c
i
s
target/
r
iscv: cpu: S
e
t XLE
N
in
d
epe
n
dent
l
y from targ
e
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
ta
r
get/riscv
:
csr: Remove compile time XLEN
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Fran
c
is
target/r
i
s
c
v: cpu_helper: Re
m
ov
e
c
o
mpile time XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fra
n
c
i
s
target/riscv:
cpu: R
e
move compil
e
time
X
L
EN ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair
Fr
a
nc
i
s
t
arge
t
/riscv: Specify the XLEN
f
or CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/ri
s
cv: Add a
r
is
c
v_cpu_is_32bit() helper functi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
anci
s
target/risc
v
:
fpu_
h
elper: Match
f
unctio
n
defs in HELPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fran
c
is
h
w
/riscv: sifive
_
u: Remo
v
e co
m
pile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Fr
a
ncis
hw/riscv
:
spike
:
R
e
m
ove comp
i
le time XLEN chec
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair
F
r
ancis
hw/risc
v
:
vir
t
: Rem
o
ve
co
m
pile time XLEN ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Franc
i
s
hw/riscv:
b
oot: Remove compile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
F
ranc
i
s
riscv: virt
:
Remove target macro conditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
ista
i
r F
r
ancis
riscv
:
spike: R
e
move target ma
c
ro
c
o
nditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Francis
targe
t
/
r
iscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Franc
i
s
hw/riscv: Expand the i
s
32-bi
t
check to support mo
r
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
i
ntc/
i
bex_plic: Clear interrupts that occu
r
during
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
Alistair Francis
regi
s
ter: Remove unnec
e
ssary
NULL check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
A
l
istair
F
rancis
i
n
t
c/i
b
e
x_plic: Ensure we don't loose inter
r
upts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
intc/ibex
_
plic: Fix some typos in
the
comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alis
t
air Francis
hw/
i
ntc/
i
bex_plic
:
Clea
r
the c
l
aim regis
t
er w
h
en
r
e
ad
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
Francis
target/ris
c
v: Spli
t
the Hypervisor execute load
h
elpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
listair
Fr
a
ncis
t
a
rget/riscv: Remove the hy
p
load a
n
d
st
o
re f
u
nct
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
target/riscv:
Remove the HS_TWO_S
T
AGE f
l
ag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair
Fr
a
n
cis
target/
r
iscv: Set
the virtualised MMU
m
ode when doing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Ali
s
tair F
r
anci
s
target/riscv: Add a
v
irtualised
M
MU Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
A
listair
F
r
a
nc
i
s
linux-user/sysca
l
l: Fix
m
i
ssin
g
target_to_
h
ost_timespec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
listair Francis
hw/riscv: Load the ker
n
e
l a
f
ter the fi
r
mware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Al
i
s
tair Fr
a
n
c
is
hw/riscv: Add a riscv_is_32_bit() functio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
l
ista
i
r Francis
hw/riscv: Return the end addres
s
o
f
the l
o
ade
d
firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
h
w/riscv: sifiv
e
_u: Allow speci
f
ying the
C
PU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
t
air Francis
ris
c
v:
C
o
nvert interru
p
t
l
ogs to use qemu_lo
g
_mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
listair
Fra
n
cis
core/regi
s
t
e
r:
S
pecify instance
_
si
z
e
in the TypeInfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Francis
tar
g
et/r
i
scv: Support the V
i
rtual Instruction faul
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
st
a
ir Fran
c
is
targ
e
t/r
i
scv:
Return the exception
fr
o
m invalid
CS
R
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/r
i
scv:
Supp
o
rt
t
he v0
.
6
Hypervisor extensi
o
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/
r
iscv:
O
n
ly suppo
r
t little en
d
ian guests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv: Only s
u
ppo
r
t
a s
i
ngle
V
SXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair Francis
target/riscv: U
p
da
t
e
t
he CSRs to the
v
0
.
6 Hyp extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
i
r
Francis
target/riscv: Update the H
y
per
v
iso
r
t
rap return/e
n
t
ry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franci
s
target/riscv:
Fix t
h
e interrupt ca
u
se
c
ode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
ra
n
cis
targ
e
t/riscv: Convert MSTA
T
US MTL to
G
VA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
ra
n
cis
targe
t
/risc
v
:
Don't allow
g
u
e
s
t to write to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
r
a
ncis
ta
r
ge
t
/riscv: Do
t
wo-stage lo
o
k
u
ps on hlv/hlvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fra
n
ci
s
target/
r
iscv: Allow ge
n
er
a
t
i
ng hlv/hlvx/hs
v
instr
u
ctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/ris
c
v: Allow setting a
two-stage lookup in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair
Fr
a
ncis
h
w
/intc: ibex_pli
c
: H
o
nour source pr
i
o
r
it
i
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Al
i
s
t
air Fra
n
cis
hw/intc:
i
b
ex_p
l
ic: D
o
n't allow
r
epeat inte
r
rupts
on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/intc: ibex_plic:
U
pd
a
te th
e
pen
d
ing irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alista
i
r Francis
hw/sd/pl181: Re
p
lace f
p
rintf(stde
r
r, "*\n
"
)
wi
t
h
e
rror_r
e
port()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
A
l
i
s
tair Fr
a
ncis
hw/char:
Convert the Ibex UART to
u
s
e
t
h
e registerfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Ali
s
tair Francis
h
w
/char:
C
onvert the
Ib
e
x UA
R
T t
o
us
e
th
e
qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alist
a
ir
Franci
s
hw/ris
c
v
: Al
l
ow 6
4
bi
t
access t
o
SiFive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Francis
target/riscv: Use
a sm
a
ller guess s
i
ze for n
o
-MMU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
nci
s
riscv/open
t
itan: Co
n
nect th
e
UA
R
T
d
evice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistai
r
Franc
i
s
ris
c
v/o
p
enti
t
an
:
Con
n
e
c
t th
e
PL
I
C
de
v
i
ce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franc
i
s
hw/intc: Initial commit of lowRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
lis
t
air Francis
hw/char: Initial commit of Ibex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fran
c
is
riscv/opentitan: Fix t
h
e R
O
M size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
i
stair
Francis
target/riscv: I
m
plement
checks for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
ta
r
get/r
i
scv:
Move
the hf
e
nce instru
c
t
i
o
n
s to
the rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
rancis
target/riscv: Report
e
r
r
or
s
validating 2nd-stage
PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
ta
r
get/riscv: Set access as data_
l
o
a
d
when validat
i
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair Fra
n
cis
s
ifive_e: S
u
p
port the
r
evB
machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
t
a
ir Francis
riscv: In
i
tial commit of Open
T
i
tan mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alis
t
air Fra
n
cis
tar
g
et/ri
s
cv: Add
t
he lowRISC I
b
ex
CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fra
n
ci
s
target/riscv
:
Don'
t
set
P
MP feature in
t
h
e cpu in
i
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alista
i
r Francis
ta
r
get/riscv: Disable the MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stair Francis
targ
e
t/r
i
s
c
v: Don't o
v
erwrite th
e
reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
ista
i
r Francis
r
i
scv/boot: Add a missi
n
g header i
n
clude
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
riscv: sifive_e: Manually
d
efine t
h
e machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fr
a
ncis
d
ocs: deprecate
d
: Updat
e
t
he -bios document
a
t
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fran
c
is
t
a
r
get/riscv: Drop s
u
pport fo
r
ISA spec ve
r
s
io
n
1
.
0
9
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fr
a
ncis
target/ri
s
c
v
:
Remove the de
p
recated CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Franc
i
s
hw/riscv: spike:
Remove deprecated ISA spec
i
fic machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair
F
rancis
r
i
s
c
v
:
AND stage-1 and stage
-
2 protect
i
on flag
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alista
i
r Francis
r
iscv: Do
n
'
t
use stage
-
2
PTE lookup prote
c
ti
o
n flags
Signed-off-by:
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<alistair.francis@wdc.com>
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2020-04-29
Alistair
Francis
r
iscv/sifive_u: Add a serial prope
r
ty to the
sifiv
e
_u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair
Francis
riscv/s
i
fi
v
e_u: Fix up file orde
r
ing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Alistair Francis
li
n
ux
-
u
ser: Support futex_
t
ime64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alis
t
ai
r
F
r
ancis
l
i
nux-u
s
er/riscv: Update the sys
c
all_nr's to the 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
A
listair Fra
n
cis
linu
x
-user/syscall:
A
dd s
u
ppor
t
fo
r
clock_gett
i
me64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistair Fran
c
is
linux-user: Protect m
o
r
e
s
yscall
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-17
Ali
s
tair
Francis
target/riscv: Correctly implement TSR trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fr
a
nci
s
target/
r
iscv: Allow e
n
ab
l
i
ng
t
he H
y
p
e
rvisor
e
xte
n
sion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistai
r
F
r
ancis
t
a
rget/riscv: A
d
d the MSTATUS_
M
PV_IS
S
ET
helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
lis
t
a
i
r Francis
t
a
rget/ri
s
c
v
:
Add support for the 32-
b
it
M
STATUSH C
S
R
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Franci
s
target/
r
iscv: Set htva
l
and mtval2 on exec
p
tions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair
F
r
a
n
cis
tar
g
et/ri
s
cv
:
Rai
s
e the new execptio
n
s w
h
en
2nd s
t
age
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
targe
t
/
riscv: Imple
m
ent se
c
ond s
t
age MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alista
i
r Fr
a
ncis
target
/
riscv: Allow specif
y
ing MMU stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fran
c
is
t
arget/
r
iscv: Respect
M
PRV an
d
SP
R
V
for f
l
oat
i
ng point
ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Al
i
stair Franc
i
s
target/riscv:
M
ark both sstatus and
msstatus_hs
as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alis
t
air Francis
target/ri
s
cv: D
i
sable gu
e
st FP suppo
r
t b
a
sed
o
n vi
r
tual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alista
i
r Francis
target/riscv
:
Only set
T
B
fla
g
s w
i
th
FP sta
t
us if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair F
r
ancis
target/riscv: Remo
v
e
th
e
hret i
n
stru
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target
/
ris
c
v: Add hfenc
e
instr
u
ctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fran
c
is
targe
t
/riscv:
Add
H
y
per
v
iso
r
trap ret
u
rn
s
u
pport
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alis
t
air Fr
a
nc
i
s
target/ris
c
v: Add h
y
pvervisor
t
r
a
p support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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