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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
2020-02-27
Alistair Francis
t
arge
t
/
riscv: Ge
n
e
rate illegal in
s
tru
c
ti
o
n on WFI when V=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
F
ran
c
is
target
/
ric
s
v:
F
lush the TLB on virtulisation mode changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
ancis
target/riscv: Add suppo
r
t
for virtual interrupt setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: Exte
n
d the SIP CSR to s
u
pport virtulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
is
ta
r
ge
t
/riscv: Extend
th
e
MIE CSR
to su
p
port virtul
i
s
at
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
lista
i
r Fran
c
is
target/
r
isc
v
: Set VS b
i
ts in m
i
deleg for Hyp e
x
tension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Franci
s
ta
r
get/r
i
scv
:
A
dd virtu
a
l registe
r
swapping function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
sta
i
r Francis
target/riscv: Add Hypervisor
mac
h
ine CSRs a
c
c
esse
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
lista
i
r Francis
target/
r
iscv: Add Hyperviso
r
vir
t
ual CSRs access
e
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
targe
t
/ri
s
cv: Add Hypervisor CSR ac
c
ess functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
stai
r
Francis
target/riscv: Du
m
p
Hyper
v
isor r
e
gisters if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fran
c
i
s
tar
g
e
t/riscv:
Print priv an
d
virt
i
n disas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fra
n
c
is
target/riscv:
F
i
x CSR perm checking for HS mod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
i
s
tair
F
rancis
target/riscv: Add the fo
r
ce HS exceptio
n
mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Franc
i
s
tar
g
e
t
/riscv: Add the v
i
rt
u
lis
a
t
i
on mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: Renam
e
th
e
H irqs to
V
S irq
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r F
r
a
nc
i
s
ta
r
get/
r
iscv: A
d
d
support for
t
h
e n
e
w
execpti
o
n
numbers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
listai
r
Francis
targ
e
t/riscv: Add the Hyper
v
isor CSRs to
CPUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franc
i
s
ta
r
get/riscv:
Add th
e
Hypervis
o
r exten
s
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair
Fran
c
is
targe
t
/riscv
:
Convert MIP CSR to tar
g
et_
u
long
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
hw/arm:
Add the Netduino Plus
2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Fr
a
ncis
h
w
/arm: A
d
d the STM3
2
F4xx SoC
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
hw
/
misc:
A
dd the STM32F4xx EXTI devi
c
e
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
A
l
istair Francis
h
w
/misc: Add
th
e
S
TM32F4xx
Sysconfig devi
c
e
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Francis
r
i
scv/virt: Incre
a
se f
l
ash
s
ize
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
list
a
ir Francis
opensbi: Upgrade
from v0
.
4 to
v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
l
istai
r
F
r
a
n
cis
t
arget/riscv: Rem
o
ve atomic ac
c
esses
t
o
MIP CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
l
istair
Francis
r
i
scv/boo
t
: Fix
p
o
ssi
b
le memory le
a
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alis
t
air Francis
r
i
s
cv/
v
irt: J
u
mp
to pflas
h
if
s
pecified
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
listair Francis
ris
c
v/virt: Add the PFlash CF
I
01 de
v
i
ce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Franc
i
s
riscv/virt: Ma
n
ually defi
n
e
the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Francis
r
iscv/sif
i
ve_u: Add t
h
e
start-in-flash property
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Ali
s
tair Fra
n
c
is
riscv/sif
i
v
e
_u
:
Manually de
f
i
n
e the m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Al
i
stair Fran
c
is
riscv/sifive_u: Add Q
S
PI memory region
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Franci
s
riscv/sifive_u:
Add L2-
L
IM cache memory
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Al
i
stair Fr
a
ncis
target/ri
s
cv:
U
se TB_F
L
A
G
S_MS
T
AT
U
S_FS for floating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Fra
n
c
i
s
ta
r
get/riscv: Fix
m
status dirty mas
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair
F
rancis
target/ris
c
v
:
Upda
t
e the Hypervisor CSRs to v0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Francis
ta
r
get/r
i
s
c
v: Create function
to test
if FP is enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alista
i
r Francis
ri
s
cv: p
l
ic: Remove un
u
sed interrupt fu
n
ct
i
on
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-26
Al
i
stair Fran
c
is
riscv/b
o
ot
:
Fixup the RISC
-
V firmware w
a
rning
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-18
Alista
i
r Francis
hw/ris
c
v: Load OpenSB
I
as the default firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-18
A
l
istair
Francis
roms: Add Ope
n
S
BI versio
n
0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-09
A
l
istair Francis
tc
g
/riscv: Fix
RISC-VH
hos
t
build failure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-27
Alistair Fran
c
is
hw
/
riscv: Ext
e
nd the ke
r
nel loading support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-27
Al
i
stair Fra
n
cis
h
w/riscv: Add su
p
p
ort
for l
o
ading a firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-27
Alistair Francis
hw/riscv: Split out the
boot functi
o
ns
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
A
listair Fra
n
c
is
t
arg
e
t/riscv: Add suppo
r
t for
d
i
sabling/enabl
i
ng Cou
n
ters
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Fra
n
c
is
target/r
i
s
cv: Remove user version i
n
fo
r
mation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
A
list
a
ir Francis
tar
g
et/risc
v
: Require either
I
or
E
base extensi
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Al
i
stair Francis
qemu-de
p
r
ecated
.
t
exi:
D
eprecate
t
h
e
RI
S
C
-V pri
v
l
edge
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
A
l
istair Francis
ta
r
get/r
i
scv: Set privledge spec 1
.
1
1
.
0 as defaul
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Fran
c
is
t
a
r
get/
r
iscv: Add
the mcountinh
i
b
i
t CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-24
Alis
t
air Francis
target/risc
v
:
Add
t
he pri
v
ledge spec versi
o
n 1
.
11
.
0
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-24
A
l
i
stair
Francis
target/riscv: Restructure
depr
e
ca
t
d
CP
U
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-24
Alistair Fran
c
is
t
a
rge
t
/riscv: A
l
low
setting IS
A
extensions
v
ia CPU
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
l
istair F
r
a
n
cis
target/
r
isc
v
: A
d
d
the HG
A
TP regist
e
r masks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair Francis
target/riscv: Add the HSTATUS register
m
asks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alista
i
r Francis
targe
t
/riscv: Add Hyper
v
isor CSR
macros
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alist
a
ir
Francis
target
/
r
iscv: Allo
w
setting
m
status virtul
i
s
ation bit
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
listai
r
Francis
targ
e
t/riscv: Add
the
MPV and MTL mst
a
tus bi
t
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair
F
ran
c
i
s
target/riscv: Improve the
s
cause logic
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair
Fra
n
cis
target/riscv: T
r
ig
g
er int
e
rrupt on
M
IP upda
t
e
async
h
r
o
nousl
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alis
t
air Francis
target/riscv: Mark privilege le
v
e
l
2
a
s reserved
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alis
t
ai
r
Francis
riscv: sp
i
ke: Add a gene
r
ic
s
pike machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
listair Franci
s
target/riscv: Dep
r
ec
a
t
e the ge
n
eric no MMU CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
l
i
s
ta
i
r Fran
c
is
target/
r
iscv
:
A
d
d
a
b
a
se 32 an
d
64 bit CP
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
l
istair Fr
a
n
c
is
t
a
rget
/
riscv: Create settable CPU p
r
opertie
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair
Francis
ris
c
v
:
vi
r
t: Allow spec
i
fying
a
CPU via commandline
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
l
i
stair Fr
a
nci
s
linux-user
/
riscv: Ad
d
the CPU
t
ype as a comm
e
nt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-23
Alistair Francis
target/arm:
Fix v
e
ctor
operation
s
egfault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-09
A
l
istai
r
Fran
c
is
linux
-
user/elfl
o
ad: F
i
x
GCC 9 build warnings
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-04-04
Alistair Francis
riscv: pl
i
c: Log g
u
est errors
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-04-04
A
listair
Franci
s
riscv:
p
l
ic: Fix incorrect irq cal
c
ulation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-03-27
Alista
i
r Fra
n
cis
MAI
N
TAINERS: Updat
e
the
d
evice
t
ree maintainers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-03-19
Alistair F
r
ancis
t
a
rge
t
/
r
iscv: Remov
e
unused struct
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-03-19
Alistair Fra
n
cis
ris
c
v: sifiv
e
_u: Allow up
to 4 CPUs to be created
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-03-19
Alis
t
air F
r
ancis
riscv:
pmp: Log
p
mp access errors as guest
error
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-03-18
Alistair Fran
c
is
riscv: plic: Set
m
s
i_nonbroken a
s
t
rue
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-02-11
A
l
istair Fran
c
is
risc
v
:
E
n
s
u
re the kernel start address is
corr
e
ctly
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-02-11
Alistair Francis
R
I
SC-V: Add priv_ver to DisasContext
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2019-01-10
Alistair
F
rancis
def
a
ult-configs: Enable US
B
supp
o
rt for R
I
S
C
-V machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair
F
ranci
s
configure
:
Add support for building RISC-V host
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
A
listair Franc
i
s
disas: Add RI
S
C-V su
p
port
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
A
l
i
s
tai
r
F
rancis
t
c
g: Add
R
ISC-V
cp
u
s
ignal handler
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair Francis
t
c
g
/
riscv: Add the ta
r
get i
n
it
code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair Francis
tc
g
/
r
iscv: Add the prologue generation and
r
egister
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair Franc
i
s
tcg/r
i
scv:
Add
t
h
e out op
decoder
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistai
r
Francis
tcg/riscv: Add direct load and store instru
c
tions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair
F
ran
c
i
s
tcg
/
riscv:
Add slowp
a
th loa
d
and store
i
nstructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
A
l
is
t
a
ir Francis
tcg/ri
s
cv:
Add branch and jump inst
r
uct
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair Francis
tcg/riscv
:
A
d
d the a
d
d2 and sub2 instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair Fr
a
nci
s
tcg/ri
s
cv: Add the ou
t
load and
s
to
r
e instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alis
t
ai
r
Francis
t
c
g/riscv: Add the extract
i
nst
r
u
ctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2018-12-25
Alistair Francis
tcg/riscv: Add the mov and
m
ov
i
instruction
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alistair Fra
n
cis
tcg/ris
c
v
:
Add the relocation functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Alista
i
r Francis
tc
g
/ris
c
v: Add
the instruction emitte
r
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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commitdiff
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tree
2018-12-25
Al
i
stair
Francis
t
cg/riscv:
Add th
e
i
mmediate encoders
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2018-12-25
Alistair Francis
t
cg/riscv:
A
d
d
support for t
h
e c
o
n
str
a
ints
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2018-12-25
Alista
i
r Fr
a
ncis
tcg/r
i
scv: Add the tcg targe
t
r
egisters
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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