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target/riscv: Add the ePMP feature
2021-05-11
Ali
s
tair Franci
s
target/
r
iscv: Add t
h
e
e
P
MP feature
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
ta
r
get/riscv:
Fix the PMP is l
o
cked ch
e
c
k when usi
n
g TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Franc
i
s
hw/riscv: Enable VI
R
TIO_VGA
for RISC-
V
v
irt machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
h
w
/open
t
ita
n
: Update the i
n
terr
u
p
t
layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
MAINTAINERS: Update the R
I
SC-
V
C
P
U M
a
intainers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
ncis
target/ri
s
cv:
U
se
R
IS
C
VExce
p
tion enum for CSR access
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir F
r
a
n
cis
t
arget/risc
v
:
Use the RISC
V
Exception enum
f
o
r CSR opera
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistai
r
Fran
c
is
t
arge
t
/riscv: Fix
3
2-
b
it
HS mode
acces
s
permissions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alista
i
r
Francis
tar
g
et/ri
s
cv: Use the R
I
SCVEx
c
eptio
n
e
n
um for
C
SR predicates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
F
r
ancis
t
arget/ris
c
v: Con
v
ert the R
I
SC-V exceptio
n
s
t
o an enu
m
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Alistair Francis
MAINTAINE
R
S
:
Add
a SiFive mac
h
ine section
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair Francis
linux-
u
ser/s
i
g
n
al: De
c
ode
w
ait
i
d si_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Alis
t
air Francis
risc
v
: P
a
ss R
I
SCVHartArrayState
b
y
p
o
inter
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
a
i
r Francis
riscv/op
e
nt
i
tan: U
p
date the OpenTitan
mem
o
ry layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Francis
hw/riscv:
Use
the CPU to determine if 32-
b
it
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
F
rancis
t
a
rget/riscv
:
cpu: Set XL
E
N
i
ndependently
f
rom target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
a
ir Francis
target/risc
v
: csr: R
e
mo
v
e compile time XLEN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir
F
ranci
s
target/riscv: cpu
_
h
elper:
Remove compi
l
e
time XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Francis
targ
e
t/r
i
scv:
cpu:
Remove c
o
m
p
ile time X
L
E
N ch
e
ck
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Francis
t
a
rget/riscv:
Speci
f
y
t
h
e
X
LEN for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
F
r
a
ncis
target/ri
s
cv: Add a riscv_cpu_is
_
32
b
it() helper funct
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Franc
i
s
target/risc
v
:
fpu_
h
e
lper: Match
function
defs i
n
HELP
E
R
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/
r
iscv:
s
if
i
ve_u: Remove c
o
mp
i
le t
i
me X
L
EN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
list
a
ir Fran
c
is
hw/r
i
scv
:
spike
:
Rem
o
v
e
compile time
X
LEN ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Francis
h
w/riscv: virt:
R
emove compile time
X
LEN
c
hecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Francis
hw/riscv: bo
o
t: Remove compile time XL
E
N checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Francis
r
i
s
cv:
virt: Remove
tar
g
et macro c
o
nditional
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r Francis
riscv:
s
pike: R
e
move
t
arget macr
o
condition
a
ls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/r
i
scv: Add a TYPE_RISCV_CPU_BASE
C
PU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
F
r
ancis
hw/riscv: Expand the i
s
3
2
-bi
t
check to s
u
pport more
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Francis
intc/ibex_pli
c
: Clear
i
nterrup
t
s
t
hat occur duri
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
A
l
istair
F
rancis
register: Remove unnecessary NULL check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
intc/ib
e
x_plic: E
n
s
u
re
w
e don't
l
oo
s
e inter
r
upts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
A
l
i
s
t
air Francis
intc
/
ib
e
x_plic: Fix
s
ome
t
y
pos in
the comm
e
nts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Ali
s
t
a
ir Francis
hw/intc/ib
e
x_plic: Clear the claim register when read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alis
t
a
i
r Francis
target/ri
s
cv: Spli
t
t
h
e
H
y
pervis
o
r
execute load help
e
rs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
t
arget/riscv: Remove th
e
hyp load and store functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Al
i
stair Francis
target/
r
iscv: Remove the HS_T
W
O
_ST
A
GE flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Al
i
stair Fran
c
is
targe
t
/riscv:
Se
t
the virtu
a
li
s
ed MMU mode when doing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
istair Francis
targe
t
/riscv: Ad
d
a v
i
rtuali
s
ed MMU Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alistair Fran
c
is
linux
-
u
ser/syscall: Fix missing targe
t
_to_host
_
timespec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
hw/riscv:
Lo
a
d
the kernel
a
fter
the firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair F
r
an
c
i
s
hw/riscv: Add a
ris
c
v_is
_
32_bit() fu
n
c
t
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Al
i
stair
F
ranci
s
h
w
/
riscv:
Return
th
e
end
address o
f
the l
o
a
ded fir
m
wa
r
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
l
i
stair
F
ranci
s
hw/r
i
scv: si
f
ive_u:
A
llow specifying
the CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Fr
a
ncis
ri
s
cv:
C
o
n
ver
t
interrupt logs to u
s
e qemu_log_mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
l
istair Franc
i
s
c
o
re/reg
i
ster
:
Speci
f
y
inst
a
nce_size in
the TypeIn
f
o
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
is
targ
e
t/riscv: Support the Virtual Ins
t
ruct
i
on fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
stai
r
Franci
s
t
a
rget/riscv:
R
e
t
urn the exceptio
n
from invalid CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
ista
i
r Fr
a
ncis
ta
r
g
et/
r
iscv
:
Support the v0
.
6 Hypervisor extens
i
on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
t
a
rget/riscv: Only sup
p
ort little
endian guests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fr
a
nci
s
target/riscv: Only
support
a s
i
ng
l
e VSXL
l
ength
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Al
i
st
a
i
r
Fran
c
is
target/ri
s
cv: Update t
h
e
C
SRs
t
o the v0
.
6 Hyp exten
s
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r Fran
c
i
s
ta
r
get/riscv:
Update th
e
Hype
r
v
isor trap return/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair Fra
n
cis
ta
r
g
e
t/riscv:
F
ix th
e
interru
p
t cause
c
ode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/r
i
s
c
v: C
o
nv
e
rt
M
STA
T
US MTL to
G
V
A
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
air Francis
target/risc
v
: Do
n
't allow gu
e
st to wri
t
e
to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair F
r
a
ncis
target/riscv
:
Do two-stage lookups on hlv/
h
lvx/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
i
r
Franc
i
s
tar
g
et/riscv: All
o
w g
e
nerating hlv/hlvx
/
hsv inst
r
uctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair F
r
ancis
t
a
rget/ris
c
v: Allow set
t
ing a two-stage lookup
in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
listair Francis
hw/intc:
i
bex_
p
lic: Hon
o
ur source prioritie
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
istair Francis
hw/intc: i
b
ex_plic: Don't allow
repea
t
interrupts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
i
st
a
ir Francis
hw/i
n
tc: i
b
ex_
p
lic: Update
t
he
pending irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Al
i
sta
i
r
F
rancis
hw/s
d
/pl181: Repl
a
ce f
p
rin
t
f(stderr, "*\n
"
) wit
h
error
_
re
p
o
rt()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair F
r
anci
s
hw/char: Convert the Ibex UA
R
T to use the registerfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Fran
c
is
hw/char: Convert the Ibex UART to
u
se
t
he qdev C
l
ock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair
Franci
s
hw/riscv: A
l
low 64 bi
t
ac
c
ess to S
i
Five CLIN
T
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
tar
g
e
t/
r
i
s
c
v
:
Use a
smaller guess size for no-MM
U
P
MP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
Francis
r
i
scv/opentitan
:
Connect the UART de
v
ice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
r
i
s
c
v/opentitan: Connect th
e
PLIC de
v
ice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franci
s
hw/in
t
c: Initial
c
ommit of lowRISC Ib
e
x P
L
IC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir Francis
h
w
/
c
har: Initial commit of
Ibex
UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
riscv/opentitan: Fix
t
he ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir Francis
targ
e
t/riscv
:
I
mple
m
ent
checks f
o
r hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Francis
t
arget
/
riscv:
M
ove the hfen
c
e instruc
t
io
n
s
to the r
v
h
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Ali
s
tair F
r
ancis
ta
r
g
et/riscv: Rep
o
rt er
r
o
r
s validat
i
ng 2nd
-
s
t
a
g
e
P
TEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Al
i
s
t
ai
r
Francis
targ
e
t/ri
s
c
v
: Set a
c
c
e
ss as
dat
a
_load when v
a
lid
a
tin
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alis
t
a
i
r
Francis
sifive_e:
S
u
ppo
r
t the revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Al
i
stair
F
rancis
r
i
scv: Initi
a
l c
o
mmit of Op
e
nTit
a
n ma
c
hi
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
i
stair Francis
target
/
riscv: Ad
d
the lowRISC Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alista
i
r Francis
ta
r
ge
t
/risc
v
: Don't s
e
t PMP
f
eature
i
n the cpu
i
n
it
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Franci
s
tar
g
et/riscv:
Disab
l
e
the MMU
correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Francis
tar
g
e
t
/riscv: Don't
overwr
i
te the reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
listair Franc
i
s
riscv/
b
oot: Add a missing
h
eade
r
include
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alista
i
r
Fra
n
cis
riscv: sifive_e: Manually define the ma
c
hine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
i
stair
Fr
a
ncis
d
ocs: deprecat
e
d: Update the -bios documentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Ali
s
tai
r
Fra
n
cis
targ
e
t
/ri
s
cv: Drop support for
ISA spe
c
version
1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Francis
t
a
r
get/riscv
:
R
e
move the dep
r
eca
t
e
d
CPU
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Al
i
stair Francis
hw/riscv: sp
i
ke: Re
m
ove
de
p
re
c
ated ISA spe
c
ific machin
e
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Fra
n
cis
r
i
scv
:
A
ND sta
g
e-1
a
nd stage-2
p
r
otection fl
a
gs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
Alistai
r
Francis
riscv:
D
o
n't use s
t
age-2 PTE lookup prot
e
ction
fl
a
gs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
Alistair Francis
riscv/si
f
iv
e
_u: Add a serial prop
e
rty
to th
e
sif
i
v
e_
u
SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
l
istair Francis
riscv/sifive_u: Fix up file ordering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Al
i
stair Francis
linux-user: Sup
p
ort futex_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Alistair Francis
l
i
nux-user/r
i
scv: Upd
a
te th
e
syscall_n
r
's to
t
he 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Alistair Fr
a
n
cis
linu
x
-
u
ser/sys
c
all:
A
dd support for clock_ge
t
time64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Alistair Francis
linux-us
e
r:
Prot
e
ct more sys
c
al
l
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-17
Al
i
st
a
ir Francis
targe
t
/ris
c
v:
C
o
r
rectly implem
e
nt T
S
R tra
p
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistai
r
Franc
i
s
target/riscv
:
Allow enabling the Hyperv
i
sor
e
xten
s
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Al
i
stai
r
F
r
ancis
target/riscv
:
Add the MSTA
T
US_MPV_ISSET
helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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