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target/riscv: Add the ePMP feature
2021-05-11
Alistair F
r
ancis
target/riscv:
A
d
d
the ePMP
f
ea
t
ure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
F
rancis
target/
r
iscv: Fix the
P
MP is locke
d
c
h
eck when
using TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istair Francis
h
w/r
i
scv: Enabl
e
VIRTIO_VGA fo
r
RISC-V vir
t
machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
stair Francis
h
w
/opentitan: Update
t
he interrupt
l
ayout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
ista
i
r
Francis
MAINTAINERS: Update
t
he
R
ISC-
V
CPU Maintainers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
stair Fr
a
ncis
target/riscv:
U
se RISCV
E
xc
e
ption
enum fo
r
CS
R
acc
e
ss
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
Fr
a
ncis
tar
g
et/riscv: Use
the RISCVExc
e
ption
en
u
m for CSR ope
r
ations
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
stair Fran
c
is
t
a
rg
e
t/riscv: Fi
x
32-bit HS m
o
de ac
c
e
s
s p
e
r
miss
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
li
s
tair
Francis
target
/
riscv: Use the
R
ISCVException
enum f
o
r
CSR predic
a
tes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
lis
t
a
ir Francis
ta
r
get/riscv: Convert
the RIS
C
-
V
exce
p
ti
o
n
s
t
o
an enum
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
A
l
i
stair Francis
MAIN
T
AINERS: Add
a
S
i
F
ive mach
i
ne section
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair Francis
linux
-
user/s
i
gnal: Deco
d
e
waiti
d
s
i_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Alistair Francis
riscv
:
Pass RISCVHartArrayS
t
at
e
by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Francis
risc
v
/opent
i
tan: U
p
dat
e
the
Open
T
itan mem
o
ry layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
st
a
ir
F
ranc
i
s
hw/ris
c
v:
Use the
C
PU to
determine if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Fr
a
ncis
target/riscv:
c
p
u: Set XLEN i
n
de
p
endently from
t
arget
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Fr
a
ncis
tar
g
et/r
i
scv: csr
:
Remove c
o
mpile t
i
me XLEN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
F
r
a
ncis
ta
r
get/ri
s
c
v
: cpu_helper: Remove compil
e
time X
L
EN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/riscv: cpu:
Remove
c
ompil
e
ti
m
e XLEN ch
e
c
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Francis
t
a
rget/r
i
scv: Specify th
e
X
LEN for C
P
Us
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair
F
rancis
tar
g
e
t
/riscv: Add a riscv_cpu_is_32bi
t
() helper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Francis
ta
r
g
et/riscv: f
p
u_
h
elper: Match fun
c
t
i
o
n defs in H
E
LPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/ri
s
c
v:
s
ifive_
u
: Re
m
ove
c
o
m
p
i
le time
XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
h
w
/ris
c
v: spike: Remove compil
e
time XLEN
c
hecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
stair Francis
hw/riscv: virt
:
R
emove
c
ompile
t
ime XLEN ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lis
t
ai
r
Franci
s
hw/riscv: b
o
ot: Remov
e
compile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
s
tai
r
Fra
n
cis
riscv: virt: Remove target macr
o
conditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
is
t
a
ir Fr
a
ncis
r
iscv: spike: Remove tar
g
et macro cond
i
tionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lista
i
r Fran
c
is
t
a
r
g
et/riscv
:
Add a TY
P
E
_
RISCV_CPU_BAS
E
CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
listair Francis
hw/ris
c
v
:
Ex
p
and the is 32-bit check t
o
su
p
por
t
m
o
re
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fra
n
c
is
intc/ibex_plic: Clear inte
r
rupts that occur during
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
A
l
istair Francis
register: Remove unnec
e
s
s
ary NULL check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
int
c
/ib
e
x_plic: Ensur
e
we
d
on'
t
loose interrupt
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Al
i
s
t
a
ir
Fr
a
ncis
intc/ib
e
x_plic: Fix some ty
p
os in the comme
n
ts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
istair Francis
h
w/intc/ibex_plic: Clea
r
the c
l
aim reg
i
st
e
r when read
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
listai
r
Francis
ta
r
get/risc
v
: Spl
i
t the Hypervisor e
x
ecute load
help
e
rs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Ali
s
ta
i
r
Francis
t
arget/riscv: Remove t
h
e hyp
l
oad and store
functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alist
a
ir
Franc
i
s
t
a
rge
t
/riscv:
R
emove the HS_TWO_STAGE flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair
F
r
ancis
tar
g
et/ri
s
cv: S
e
t
t
he
vi
r
tualised MMU m
o
de when d
o
ing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
lis
t
air Francis
target
/
riscv: Add a virtu
a
lis
e
d MMU Mo
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alista
i
r
F
rancis
linux-user/s
y
scal
l
:
Fix
missing
t
arget_to_host_
t
imespec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
hw
/
riscv: Load t
h
e ke
r
nel afte
r
the firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
hw/
r
iscv:
A
dd a
r
iscv_is_32_bit
(
) fu
n
c
t
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair
F
rancis
hw/r
i
scv: R
e
turn the en
d
addr
e
ss of t
h
e
loaded firmwa
r
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tair Francis
hw/r
i
scv
:
sifiv
e
_u: A
l
low specif
y
ing t
h
e CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
l
istair F
r
ancis
ri
s
cv: Convert
interrupt logs to u
s
e qemu_lo
g
_m
a
sk()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
Alistair Francis
core/register: Specify
i
n
s
ta
n
c
e_
s
ize
in t
h
e Ty
p
eInfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
is
t
ar
g
et/riscv
:
Support the Vi
r
tual Instru
c
tion fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
is
t
arget/ris
c
v: Return th
e
exception
from invalid
C
SR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
t
arget/riscv: Support the v0
.
6 Hyp
e
rvisor
ex
t
ension
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fra
n
cis
target/riscv: Only support little endian
gues
t
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
is
t
air
F
r
a
ncis
t
arget/r
i
scv
:
Only
s
upport a
s
i
ngl
e
VSXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istai
r
Francis
target/riscv:
Update the CSR
s
to the v0
.
6 Hyp
e
x
t
e
n
s
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r Francis
targ
e
t/riscv: Update th
e
Hype
r
visor trap
retur
n
/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r
Francis
t
arget/r
i
s
c
v: Fix th
e
i
n
terrupt cause
code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
ir Francis
target/riscv:
Co
n
vert MSTATU
S
M
TL
t
o
G
V
A
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
t
a
rget/risc
v
: Don
'
t
allow guest t
o
write to
htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
is
target/riscv: Do two-stag
e
l
o
o
kups on h
l
v/hlvx/hs
v
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
ta
r
get/riscv: Allow gener
a
ti
n
g
h
l
v/hlvx/hsv instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r Francis
target/
r
i
s
cv: Allow setting a
t
w
o-stage lookup in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
ist
a
i
r Francis
h
w/intc: ibex_p
l
ic: H
o
nour source prior
i
t
i
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
i
s
t
air F
r
ancis
hw/intc
:
i
bex_p
l
ic
:
Don't allow r
e
peat interrup
t
s on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair
F
rancis
hw/intc: ibex_pl
i
c: Update the pe
n
ding irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alis
t
ai
r
F
r
ancis
h
w/sd/pl181: Replace
fprintf(std
e
rr, "*\n"
)
w
ith error_report()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Francis
hw/char: Convert t
h
e Ibex UART to
use the r
e
gisterfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair
F
r
an
c
i
s
hw/ch
a
r: Convert the Ib
e
x UART to u
s
e
t
he qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Al
i
stai
r
F
r
ancis
hw/riscv:
Allow 64 bit
a
ccess to
S
i
F
ive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
rancis
t
arget/riscv: U
s
e a smal
l
er guess
s
ize for no-MMU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tair Franci
s
riscv
/
opentitan: Conne
c
t t
h
e
UART
device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alis
t
a
i
r
F
rancis
riscv/op
e
n
t
itan: Con
n
e
c
t t
h
e PLIC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/intc: Initi
a
l
commit of lowRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Francis
hw/cha
r
:
Initi
a
l commit
o
f Ib
e
x UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fran
c
is
riscv/opentitan: Fix the ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Al
i
sta
i
r Fran
c
is
target/ris
c
v: Imp
l
ement checks for hf
e
nce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Francis
target/ris
c
v:
M
o
v
e
th
e
hfence i
n
stru
c
tio
n
s
t
o the
r
vh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Al
i
stair Francis
target/riscv: Report error
s
validat
i
n
g
2
nd-stage PT
E
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
A
listair F
r
a
ncis
t
arget/risc
v
:
S
e
t access a
s
d
a
t
a_load when validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Francis
sifive
_
e: Sup
p
ort the r
e
vB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Francis
r
i
s
cv: Initial co
m
mi
t
o
f
O
pen
T
i
tan m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Francis
t
a
rge
t
/riscv: Add th
e
lowRISC Ibex
C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alista
i
r Francis
target/riscv: Don't
s
et
PMP feature in the
cpu in
i
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Francis
t
arg
e
t/riscv
:
Disab
l
e
the MMU cor
r
ectly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fr
a
ncis
target/ris
c
v: Don't over
w
r
ite the res
e
t v
e
ctor
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistai
r
F
r
a
n
c
i
s
riscv/boot: Add a mis
s
ing header incl
u
de
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
listai
r
Francis
ri
s
cv
:
sifive_e: Manuall
y
define the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-06-03
Ali
s
tair Francis
d
ocs: depreca
t
ed: Update
the -bios docum
e
ntation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair F
r
ancis
target/riscv: Drop
s
upport for ISA
s
pec version
1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fr
a
ncis
targ
e
t/riscv
:
R
emove the de
p
r
e
cated CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
istair Francis
hw/riscv: spike: R
e
mov
e
deprecated ISA specific machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Francis
r
i
sc
v
: AND stage
-
1
and s
t
a
ge-2 prot
e
ction flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
l
istair Fr
a
nci
s
r
iscv: Don't use stage-2 PTE lookup protection
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Francis
riscv/sifive_u: Add
a
serial prop
e
rty to t
h
e
s
i
fiv
e
_
u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
listai
r
F
r
ancis
riscv/sifive_u: Fix
u
p
file
o
r
der
i
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Alistair Francis
linux-user: Support futex
_
time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistair Fr
a
ncis
lin
u
x-user/riscv: Up
d
ate the syscall_nr'
s
to the
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistair
F
r
ancis
linux-user/sy
s
call: Ad
d
support
fo
r
c
l
o
ck_gett
i
me6
4
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistair Franci
s
linux-
u
ser: P
r
o
te
c
t
more sysca
l
ls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-17
Alistair Fr
a
ncis
t
a
r
get/riscv: Correctly imp
l
ement TS
R
trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target/ris
c
v
: Allow enabli
n
g the H
y
perviso
r
extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Fra
n
cis
tar
g
et/riscv: Add the MSTATUS_MP
V
_ISSET helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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