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target/riscv: Add the ePMP feature
2020-02-27
A
l
i
s
tair Fr
a
ncis
target/riscv: Add sup
p
ort for the 32-bit MSTATUSH C
S
R
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
ancis
t
a
rge
t
/riscv:
S
et ht
v
al and mtval2 o
n
e
x
ecptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air F
r
ancis
target/
r
i
scv: Rais
e
the new exe
c
ptions when 2n
d
st
a
ge
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
tair Fra
n
cis
target/riscv: Implement seco
n
d stage MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair
F
rancis
target/risc
v
:
Allow specifying
MMU s
t
age
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
F
r
an
c
is
t
arget/ri
s
cv: R
e
spect MPRV and SPRV
for float
i
ng point ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
F
r
anci
s
tar
g
et/r
i
scv
:
Mark both sstatu
s
and msstatus
_
hs
as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
target
/
riscv: Disable
gues
t
FP support based on
v
irt
u
al
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair
F
ran
c
is
target/riscv: On
l
y set TB
f
lags
w
ith FP status if
e
nabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
Francis
ta
r
get/riscv: Remove the hr
e
t inst
r
u
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franc
i
s
target/riscv: Add hf
e
nce
instru
c
tions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Franc
i
s
t
arget/riscv:
A
dd Hypervisor tr
a
p re
t
ur
n
support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Fr
a
ncis
t
arget/r
i
scv:
Add hyp
v
e
rvi
s
or trap support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
i
r Francis
target/riscv: Generat
e
i
l
legal
instruc
t
ion on W
F
I wh
e
n V=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
ancis
target/ricsv: Flus
h
the TLB on virtulisation mode ch
a
n
g
es
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
l
istair Fr
a
n
cis
t
arget/riscv: Add support
for
v
i
rtual interrupt setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair F
r
a
ncis
t
a
rge
t
/ri
s
cv:
Extend th
e
SIP CSR to support vi
r
tulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
Francis
target/ris
c
v
:
E
x
tend the M
I
E C
S
R to support vir
t
ulisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air Franc
i
s
target
/
ris
c
v: Set VS b
i
ts
in mideleg for Hyp
e
xtensio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Fr
a
ncis
target/riscv: Add virtual reg
i
ster swapping function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target
/
r
i
s
c
v: Add Hypervisor mach
i
n
e CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
i
r
Franci
s
target/riscv: Add Hyp
e
rv
i
sor virtual CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: Add Hype
r
visor C
S
R a
c
cess functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
tar
g
et/riscv: Dump Hypervis
o
r
r
egisters if
enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r Francis
target/ris
c
v:
P
rint priv and virt in disas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/risc
v
: Fix CSR
perm
checking for HS mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air Franc
i
s
targ
e
t
/riscv: Add th
e
fo
r
ce HS exception mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air Francis
target/risc
v
: Ad
d
the virtulisation mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alis
t
air
Fran
c
is
t
arget
/
risc
v
: R
e
name the H i
r
qs to VS irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
Francis
t
a
r
g
et/riscv: Add suppor
t
for the new execption numbers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistai
r
F
r
ancis
t
arget/ris
c
v: Add the Hypervisor
C
SRs to CPUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair Francis
target/riscv: Add the
Hy
p
ervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
li
s
tair Francis
tar
g
et/riscv: Co
n
vert MI
P
CSR to target_ul
o
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-01-17
A
listair Francis
hw
/
a
rm: Ad
d
the Netduino Plus 2
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Alistair Francis
hw/arm: Ad
d
t
he
S
TM32F
4
xx
S
oC
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Ali
s
tair F
r
ancis
hw
/
misc: Add the ST
M
32F4xx E
X
TI device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2020-01-17
Al
i
stair Franc
i
s
h
w
/
m
isc: Add
t
he STM32F4xx Sysconfig device
Signed-off-by:
Alistair Francis
<alistair@alistair23.me>
commit
|
commitdiff
|
tree
2019-11-14
Alistair Francis
r
i
scv
/
vi
r
t: Increase flash
siz
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
l
istai
r
Francis
opensbi: Upgrade
from v0
.
4 to v0
.
5
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-11-14
A
lista
i
r Francis
target/riscv:
Remov
e
a
tomic accesses to MIP C
S
R
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair
Fr
a
ncis
riscv/boo
t
: Fix possible memory leak
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistai
r
Francis
ri
s
cv/virt:
J
u
mp to pflash
i
f
specified
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
A
l
istair Franc
i
s
ris
c
v/virt: Add th
e
PFlash
CFI01 de
v
ice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Francis
riscv/virt: Ma
n
u
a
lly defin
e
the machi
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Al
i
stair Francis
riscv/s
i
five_u: Add the start
-
in-flash property
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alis
t
air Fra
n
c
is
r
i
s
cv/sifive_u: Manually define
the
m
a
c
hine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Francis
r
i
scv/sifiv
e
_u: Add QSPI me
m
ory region
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-10-28
Alistair Francis
riscv/sifive_u: Add L2-LIM
c
ache
m
e
mory
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Al
i
stair Francis
target/riscv: U
s
e TB_F
L
A
GS_MS
T
ATUS_FS for float
i
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alis
t
a
ir Fran
c
is
target/riscv:
F
ix
mstatu
s
d
i
rty ma
s
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Fra
n
cis
target/risc
v
: Update t
h
e Hypervisor C
S
Rs
to v0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair
F
ranci
s
t
arget/
r
iscv: Create function to test
i
f FP
is enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-09-17
Alistair Francis
riscv
:
plic: Remove u
n
used int
e
rrupt functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-26
Al
i
stair Francis
ri
s
cv
/
boot
:
F
i
x
up the
RI
S
C-V
f
irmware
warning
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-18
Alista
i
r Fr
a
n
cis
hw/
r
iscv: L
o
ad OpenSBI
a
s the default firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-18
Alistair Francis
roms: Add Open
S
BI version
0
.
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-07-09
Alis
t
a
i
r Franc
i
s
tcg/
r
iscv
:
Fix RISC-VH host
build failure
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-27
Alist
a
i
r Fra
n
c
i
s
hw/riscv: Extend the
kernel loading
s
u
p
port
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-27
Alist
a
ir Fra
n
cis
hw/riscv
:
Add support for loading a fir
m
ware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-27
Alistair
F
ranc
i
s
hw/riscv:
Split out the boot functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
A
l
i
stair Francis
target/riscv: A
d
d sup
p
ort for d
i
s
abling/enabling Counters
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistai
r
Fran
c
is
targe
t
/
r
iscv: Remov
e
user
v
er
s
i
on
inform
a
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Alistair Francis
target/risc
v
:
R
equire eit
h
er I or E base extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Ali
s
tair
F
ran
c
is
qemu-depre
c
ated
.
texi: Deprecate
t
he RISC-V privledge
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
Al
i
stair Francis
targ
e
t/riscv: Set privledge sp
e
c 1
.
11
.
0 as default
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-25
A
l
istair Francis
target/riscv: Add the mcount
i
nhibi
t
CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-24
Alistair F
r
a
n
c
i
s
ta
r
get/riscv
:
Add
the privledge spec versi
o
n 1
.
11
.
0
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-24
Alistair Francis
target/riscv: Restructure depre
c
atd CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-06-24
Alistair Fra
n
cis
targe
t
/ri
s
cv: All
o
w setting ISA
e
xt
e
nsions
via CPU
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alist
a
i
r
Francis
target/ris
c
v:
A
dd the HGATP register masks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistai
r
Francis
t
a
r
get/riscv: Add the HSTATUS reg
i
s
t
er masks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Ali
s
t
a
ir Francis
target/riscv:
A
dd Hypervisor CSR ma
c
ros
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Al
i
stair Francis
target/riscv: Allow set
t
ing
msta
t
us virtulisation
bits
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
A
l
istair Franci
s
target/r
i
sc
v
: Add the MPV and MTL mstatus bits
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair Francis
target/riscv: Improv
e
the s
c
au
s
e logic
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alist
a
i
r
Francis
targe
t
/
r
is
c
v: Trig
g
er i
n
terru
p
t o
n
MIP
update asynchron
o
usly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair
F
rancis
target/ris
c
v:
M
ark privilege level 2 as r
e
served
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair Franc
i
s
riscv: spike: Add a
ge
n
eric spike
m
achine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2019-05-24
Alistair Franci
s
t
arget/riscv
:
Deprecate
t
he g
e
neric no MM
U
C
P
Us
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Ali
s
ta
i
r Fran
c
is
t
a
r
g
e
t/riscv: Add a base 32 and 64 b
i
t CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Alist
a
ir Francis
tar
g
et/ri
s
c
v
: C
r
eate settabl
e
CPU properties
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Ali
s
tair Fran
c
is
riscv: virt:
Allow sp
e
ci
f
yin
g
a CPU via c
o
m
mandl
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-24
Alistai
r
F
r
ancis
linux-user/r
i
scv: Add the CPU type as a
comment
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-05-23
A
l
i
stair Francis
targe
t
/
arm: Fix vector operation segfaul
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2019-05-09
Ali
s
ta
i
r Francis
linux-user/elfload: Fix GCC 9 build warni
n
gs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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commitdiff
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tree
2019-04-04
Alistair Francis
r
iscv: p
l
i
c
: Lo
g
g
u
e
st
errors
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-04-04
A
l
i
sta
i
r Franci
s
riscv: plic
:
Fix incor
r
ect irq calcu
l
a
t
ion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-03-27
Alista
i
r Fr
a
n
cis
MAINTAINERS: Update the device tree maintai
n
ers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-03-19
A
l
ist
a
i
r
Fran
c
is
target/riscv: Remove unused struct
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-03-19
Alista
i
r F
r
a
nci
s
r
i
scv
:
si
f
iv
e
_
u
: Al
l
ow up to 4 CPUs to be create
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-03-19
Alistair Fran
c
is
riscv
:
pmp: Lo
g
p
m
p
access erro
r
s a
s
gu
e
st
e
rrors
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-03-18
Alistair Francis
riscv: plic: Set msi_nonbroken a
s
tr
u
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-02-11
Alistair Francis
riscv: Ensure the
k
ernel sta
r
t address
i
s
c
or
r
ec
t
l
y
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-02-11
Alistair Fran
c
is
RISC-V: Add p
r
i
v
_ver to Di
s
asContext
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2019-01-10
Alist
a
ir
F
rancis
default-conf
i
gs: Enable USB support
for RISC-V machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2018-12-25
A
l
ista
i
r Francis
configu
r
e: Add support for building RIS
C
-V host
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2018-12-25
Al
i
sta
i
r
Fr
a
n
c
is
disas
:
Add RISC-V suppor
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2018-12-25
Alistair Francis
t
c
g
:
A
d
d RISC
-
V cpu si
g
nal
ha
n
dler
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2018-12-25
Alist
a
ir Fran
c
is
tcg/ris
c
v
: Add the
t
arget init
c
o
d
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2018-12-25
Al
i
stair Fra
n
c
is
tcg/r
i
scv: Add the p
r
ol
o
gue generation and register
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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