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target/riscv: Use the RISCVException enum for CSR predicates
2021-05-11
Alis
t
ai
r
F
ranc
i
s
tar
g
et/r
i
scv: Use
t
he
RISCVE
x
ception enum for CSR predicates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Francis
targ
e
t
/
riscv: Conve
r
t th
e
RISC-V exceptions
to
an en
u
m
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Alistair F
r
ancis
MAINTAINERS
:
Add a
SiFive machine
s
e
ct
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistair Francis
lin
u
x-user/signal: Decode
w
ai
t
id
s
i_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Ali
s
tair Francis
riscv:
Pass
RISCVHartArrayS
t
ate by
p
o
inte
r
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Francis
riscv/opentita
n
: Update
t
he OpenTitan mem
o
ry
layou
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fra
n
cis
hw/ris
c
v:
U
s
e
t
he CPU to dete
r
mine if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Franci
s
targe
t
/riscv: cpu: Set
XLEN
i
ndepende
n
t
l
y
from tar
g
et
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/riscv:
csr
:
Rem
o
ve compile time XLEN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Francis
target/risc
v
: c
p
u_he
l
p
er: Remove compile
t
i
m
e XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Francis
target/riscv: cpu: Remove compile time
XL
E
N chec
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
i
r
Francis
targe
t
/riscv: Speci
f
y the XLEN for CPU
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
tar
g
et/riscv:
Add a riscv_cpu_is_32bit() h
e
lper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair F
r
ancis
t
arget/riscv: fpu_h
e
lper: Match
function defs in HELPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
s
tair Fran
c
is
hw/riscv: sif
i
ve_
u
: Remove co
m
pile time XL
E
N
ch
e
cks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tair Francis
hw
/
riscv
:
s
p
ike: Remove co
m
pile time XLEN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fran
c
is
hw/riscv: vi
r
t: Remo
v
e compile tim
e
XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r Francis
hw/risc
v
: boot:
R
e
move com
p
ile time XLEN
ch
e
c
ks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir Francis
riscv: vir
t
: Remo
v
e
t
a
rget macro conditiona
l
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
riscv: sp
i
ke: Remove target macro
conditiona
l
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
t
air Franc
i
s
targ
e
t/r
i
scv: Add a TYPE_RISCV_CP
U
_BASE CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fran
c
i
s
hw
/
riscv:
E
xpand the is
32-bit check
t
o sup
p
ort mor
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alis
t
air Fran
c
is
intc/ibex_
p
lic: Clea
r
i
n
terr
u
pts that occur
durin
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
Alistair Fra
n
cis
register: R
e
mov
e
u
n
necessary NULL check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
intc/ibex_
p
l
ic: Ens
u
r
e we do
n
't lo
o
se interrupts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
A
listair Francis
int
c
/ibex_pl
i
c:
Fix some typos in the comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair
F
ra
n
c
is
hw/
i
ntc/ibex_plic: Clea
r
the claim register when rea
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Al
i
s
tair Fran
c
i
s
t
ar
g
et/riscv: Spl
i
t the Hypervisor
e
xecute load h
e
lpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
ista
i
r Franc
i
s
t
a
rget/
r
iscv: Rem
o
ve the hyp
load and store functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
F
r
ancis
targ
e
t
/
riscv: R
e
move
the HS
_
T
WO_STAGE fla
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Fra
n
c
is
target/riscv: Set
t
he
v
irtualised MM
U
mode when
d
oing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
F
rancis
target/riscv: Add
a
vi
r
t
u
a
lised MMU Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alist
a
ir Francis
linux-user/syscall:
Fix m
i
ssing targ
e
t_to_host_t
i
mespec6
4
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tai
r
Fr
a
ncis
hw/riscv
:
Load t
h
e kernel a
f
ter
t
h
e firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair
F
rancis
hw/riscv:
Add
a ri
s
c
v
_
is_32_bit() function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alist
a
ir Francis
hw/riscv: Return
the en
d
addres
s
of the loaded firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistai
r
F
rancis
hw/r
i
sc
v
: sifive_u: Allow specifying th
e
CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Al
i
stair
F
rancis
riscv: Co
n
v
ert
i
nte
r
rupt logs to use qemu_log_mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
Alistair Fran
c
i
s
c
o
re/register
:
Specify ins
t
ance_size in the
Typ
e
Info
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
i
s
t
a
rg
e
t/risc
v
: Sup
p
or
t
the V
i
rtual Inst
r
u
ct
i
on fa
u
l
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
r
ancis
targe
t
/riscv: R
e
t
urn the
e
xception from invalid CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
air F
r
ancis
target/ris
c
v:
S
upp
o
rt the v0
.
6
H
yperv
i
sor extension
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
tar
g
et/riscv: Only
s
upp
o
rt littl
e
endian gu
e
sts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
air F
r
ancis
targe
t
/riscv: Only support a single VSXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/
r
iscv: Upda
t
e
t
he
CSRs to
the v
0
.
6 Hyp
e
xtens
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistai
r
Francis
target/riscv
:
U
pdate the Hyperviso
r
t
rap ret
u
rn/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
t
a
ir Francis
target/riscv: Fix th
e
interrupt cause code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair Francis
targe
t
/riscv: Con
v
ert MSTATUS MTL to GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
targe
t
/risc
v
:
Don't a
l
low
gues
t
to wr
i
te
t
o h
t
inst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Fra
n
cis
target/
r
isc
v
: Do two-
s
tage
l
oo
k
u
p
s
on hlv/hlvx/hs
v
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r
Francis
t
a
rg
e
t/riscv: Allow generating hlv/hlvx/hsv instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair Francis
target/ri
s
cv: Allo
w
sett
i
ng a two
-
st
a
g
e
lo
o
kup in the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/intc: ibex_p
l
i
c
: Honour so
u
rc
e
prioritie
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/intc: ibe
x
_plic: Don'
t
all
o
w
r
e
p
eat
in
t
e
rrupts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
istair Francis
hw/intc: ibex_plic: U
p
date th
e
pending ir
q
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Al
i
stair Francis
hw/sd
/
pl181: Rep
l
ace f
p
rintf(
s
tderr, "*\n") with error_report()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Fra
n
cis
h
w/c
h
ar:
Conver
t
th
e
I
bex
U
ART
to use the regist
e
rfields
A
PI
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Francis
hw
/
c
h
ar: Conver
t
t
he I
b
e
x UART to
us
e
t
h
e qdev Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair Fr
a
n
ci
s
hw/riscv: Allow
6
4 b
i
t acce
s
s t
o
S
i
Five CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
ranci
s
target/r
i
s
c
v: Use a smalle
r
guess size f
o
r
no-M
M
U
PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair F
r
ancis
riscv/opentit
a
n
: Conn
e
c
t
t
he UART device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
i
r Fr
a
n
cis
r
iscv/opentitan: Connect
t
he PLIC
de
v
ice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
istair
F
r
a
nci
s
hw/intc: Initia
l
commit of lowRI
S
C Ibex P
L
IC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franci
s
h
w
/
c
har:
I
nitial commit of Ibex
UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r F
r
a
n
cis
riscv/o
p
entitan: Fix the ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r Fra
n
cis
ta
r
get/riscv: Implement checks for hf
e
n
ce
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
t
air Fr
a
ncis
targe
t
/
riscv:
Mo
v
e the
hfence instructions t
o
th
e
rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair
F
rancis
target/riscv: Report errors validating 2nd-
s
t
a
g
e
PT
E
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair Francis
t
a
r
g
e
t
/
r
iscv: Se
t
a
c
cess as data_loa
d
when v
a
lidating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair
F
rancis
sifive_e:
S
uppor
t
the
rev
B
mach
i
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
ris
c
v: Initi
a
l commit of OpenT
i
tan
m
achine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair F
r
a
n
cis
ta
r
g
e
t/ris
c
v: Add the lowRISC Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Francis
targe
t
/ris
c
v: Don't set P
M
P fea
t
u
re in
t
h
e
cpu
init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
Fr
a
ncis
targ
e
t/ris
c
v
: Disable the MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alist
a
ir
Francis
target/ri
s
cv: Don't overwrite the re
s
et
v
ec
t
or
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistai
r
Francis
riscv/bo
o
t: Add a
missing hea
d
er include
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-06-03
A
listair
F
rancis
ri
s
c
v
: sifive_e: Manually define the mach
i
ne
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Francis
do
c
s:
deprecated: Update the -bios doc
u
mentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistai
r
Franc
i
s
tar
g
et/
r
iscv
:
Drop suppor
t
for I
S
A
spec version 1
.
0
9
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistai
r
F
r
a
ncis
target/risc
v
:
Remove the
dep
r
ecate
d
CP
U
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Ali
s
tair Fran
c
i
s
hw/riscv: spike: R
e
move
de
p
rec
a
ted ISA specific ma
c
hines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
l
ista
i
r Fra
n
cis
riscv:
A
ND stage-1 and st
a
g
e-2 prote
c
tion
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Francis
ris
c
v: Do
n
't use stag
e
-2
P
TE lo
o
kup
protection flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Fran
c
is
riscv/
s
i
f
ive_u: Add a seria
l
property t
o
the sifi
v
e
_
u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
A
list
a
ir
F
ranc
i
s
risc
v
/sifive_
u
:
Fix up fi
l
e or
d
ering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
Alist
a
ir Fr
a
n
c
i
s
li
n
ux
-
user: Suppo
r
t
fu
t
ex_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Alistair Fran
c
is
linux-u
s
er/riscv:
U
pdate the sysc
a
ll_nr's
t
o t
h
e 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-20
Alistair
F
ra
n
ci
s
linux
-
user/syscall: Add sup
p
ort for cl
o
ck_get
t
im
e
64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
A
l
is
t
air Franc
i
s
linux-user: Protect
m
ore syscalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-03-17
Alist
a
ir Fr
a
n
c
is
targe
t
/
r
iscv: Correctly imp
l
e
m
ent TSR
trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
listair Fra
n
cis
target/ris
c
v: Al
l
ow
en
a
b
ling t
h
e Hypervisor extensio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Francis
target/ris
c
v: A
d
d
the MSTATUS
_
MPV_ISSET
h
e
l
p
er macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Francis
t
arget/r
i
scv: A
d
d
suppor
t
f
or t
h
e 32
-
bit MSTATUSH
CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Fran
c
is
target/riscv: S
e
t
h
tval a
n
d
m
t
val2
on execption
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alist
a
ir F
r
ancis
target/riscv: Raise the new exec
p
tions when 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistai
r
F
r
ancis
target/riscv: Implemen
t
seco
n
d st
a
ge MMU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair F
r
anc
i
s
t
arget/
r
iscv: Allow speci
f
yin
g
MMU s
t
age
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
l
i
stair Francis
targ
e
t/riscv: Respe
c
t MPRV
a
nd
SPRV for floatin
g
point ops
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
A
lis
t
air Fr
a
nc
i
s
target/riscv: Mark both ssta
t
u
s and mssta
t
us_hs as
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Francis
tar
g
et/riscv: D
i
sa
b
l
e guest FP support based on virt
u
al
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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