2023-06-13 | Weiwei Li | target/riscv: Make RLB/MML/MMWP bits writable only... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Change the return type of pmp_hart_has_privs... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Make the short cut really work in pmp_hart_has... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Move pmp_get_tlb_size apart from get_physical_... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Update pmp_get_tlb_size() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv: rework write_misa() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: validate extensions before riscv_timer_i... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: add priv_spec validate/disable_exts... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Update check for Zca/Zcf/Zcd Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Mask the implicitly enabled extensions... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv: add PRIV_VERSION_LATEST Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: remove set_priv_version() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: remove set_vext_version() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: add riscv_cpu_validate_v() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Weiwei Li | target/riscv: Move zc* out of the experimental properties Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-06-13 | Daniel Henrique... | target/riscv/vector_helper.c: skip set tail when vta... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Rahul Pathak | target/riscv: add Ventana's Veyron V1 CPU Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Alexandre Ghiti | riscv: Make sure an exception is raised if a pte is... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Irina Ryapolova | target/riscv: Fix Guest Physical Address Translation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Bin Meng | target/riscv: Restore the predicate() NULL check behavior Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: add TYPE_RISCV_DYNAMIC_CPU Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: add query-cpy-definitions support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: add CPU QOM header Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Ivan Klokov | hw/intc/riscv_aplic: Zero init APLIC internal state Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Reorg sum check in get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Reorg access check in get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Merge checks for reserved pte flags Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Don't modify SUM with is_debug Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Suppress pte update with is_debug Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Move leaf pte processing out of level... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Hoist pbmte and hade out of the level... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Hoist second stage mode change to callers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Check SUM in the correct register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Move hstatus.spvp check to check_access_hlsv Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Introduce mmuidx_2stage Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Introduce mmuidx_priv Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Introduce mmuidx_sum Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Handle HLV, HSV via helpers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Use cpu_ld*_code_mmu for HLVX Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Fei Wu | target/riscv: Reduce overhead of MSTATUS_SUM change Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Fei Wu | target/riscv: Separate priv from mmu_idx Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | LIU Zhiwei | target/riscv: Add a tb flags field for vstart Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Richard Henderson | target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | LIU Zhiwei | target/riscv: Encode the FS and VS on a normal way... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | LIU Zhiwei | target/riscv: Add a general status enum for extensions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | LIU Zhiwei | target/riscv: Extract virt enabled state from tb flags Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Yi Chen | target/riscv: fix H extension TVM trap Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Use check for relationship between Zdinx... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Legalize MPP value in write_mstatus Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Use PRV_RESERVED instead of PRV_H Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Fix the mstatus.MPP value after executing... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv/cpu.c: redesign register_cpu_props() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: add RVG and remove cpu->cfg.ext_g Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cp... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove riscv_cpu_sync_misa_cfg() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_v Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_j Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_h Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_u Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_s Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_m Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_e Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_i Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_f Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_d Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_c Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove cpu->cfg.ext_a Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: introduce riscv_cpu_add_misa_properties() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: remove MISA properties from isa_edata_arr[] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Daniel Henrique... | target/riscv: sync env->misa_ext* with cpu->cfg in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | hw/riscv: Add signature dump function for spike to... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Fix lines with over 80 characters Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Fix format for comments Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Fix format for indentation Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Remove riscv_cpu_virt_enabled() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Set opcode to env->bins for illegal/virtual... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Fix addr type for get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Remove redundant parentheses Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | LIU Zhiwei | target/riscv: Convert env->virt to a bool env->virt_enabled Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Remove redundant check on RVH Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Remove redundant call to riscv_cpu_virt_enabled Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | LIU Zhiwei | target/riscv: Fix itrigger when icount is used Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: Add support for Zce Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | disas/riscv.c: add disasm support for Zc* Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: expose properties for Zc* extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add support for Zcmt extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add support for Zcmp extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add support for Zcb extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add support for Zcd extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add support for Zcf extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add support for Zca extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Weiwei Li | target/riscv: add cfg properties for Zc* extension Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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2023-05-05 | Conor Dooley | target/riscv: fix invalid riscv,event-to-mhpmcounters... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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