| commit | 64f4b541c52d3ea581e9123b5bab8b915323e76d | |
| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
| Thu, 6 Apr 2023 18:03:46 +0000 (6 15:03 -0300) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 5 May 2023 00:49:50 +0000 (5 10:49 +1000) | ||
| tree | 9c1d6be9c306f66dfbbdd123bb8e2e502c0262b8 | treesnapshot (tar.gz zip) |
| parent | b5c042e8a0300989b7e9ce0d24b6535c77439d3e | commitdiff |
target/riscv: remove cpu->cfg.ext_j
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory |