| commit | ffffd954ba168d5b6812d25b8cf49d160874f241 | |
| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
| Thu, 6 Apr 2023 18:03:38 +0000 (6 15:03 -0300) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 5 May 2023 00:49:50 +0000 (5 10:49 +1000) | ||
| tree | 4c19a0e84694c102d71c2d4dea4f257e97f030c5 | treesnapshot (tar.gz zip) |
| parent | c00226e1f0620fda90c985631b31afe2a87f7e97 | commitdiff |
target/riscv: remove cpu->cfg.ext_d
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory |