| commit | 427d8e7dd871a747727dbbfef22041fedef2ee32 | |
| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
| Thu, 6 Apr 2023 18:03:41 +0000 (6 15:03 -0300) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 5 May 2023 00:49:50 +0000 (5 10:49 +1000) | ||
| tree | dd568f474c7b730adce5de6575fb11910ba6145b | treesnapshot (tar.gz zip) |
| parent | 74828eabf2c301ff93fee297519d25e0f1804b2a | commitdiff |
target/riscv: remove cpu->cfg.ext_e
Create a new "e" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
replaced with riscv_has_ext(env, RVE).
Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Create a new "e" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
replaced with riscv_has_ext(env, RVE).
Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory | |
| target/riscv/insn_trans/trans_rvzce.c.inc | diffblobblamehistory |