From 427d8e7dd871a747727dbbfef22041fedef2ee32 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Thu, 6 Apr 2023 15:03:41 -0300 Subject: [PATCH] target/riscv: remove cpu->cfg.ext_e Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - target/riscv/insn_trans/trans_rvzce.c.inc | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f082748569..33db4fa4b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -831,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) env->misa_ext_mask = env->misa_ext; } - if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { error_setg(errp, "I and E extensions are incompatible"); return; } - if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { error_setg(errp, "Either I or E extension must be set"); return; @@ -1150,7 +1150,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_has_ext(env, RVI)) { ext |= RVI; } - if (riscv_cpu_cfg(env)->ext_e) { + if (riscv_has_ext(env, RVE)) { ext |= RVE; } if (riscv_cpu_cfg(env)->ext_m) { @@ -1503,6 +1503,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVF, .enabled = true}, {.name = "i", .description = "Base integer instruction set", .misa_bit = RVI, .enabled = true}, + {.name = "e", .description = "Base integer instruction set (embedded)", + .misa_bit = RVE, .enabled = false}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1525,7 +1527,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), @@ -1644,7 +1645,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext != 0) { - cpu->cfg.ext_e = misa_ext & RVE; cpu->cfg.ext_m = misa_ext & RVM; cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_s = misa_ext & RVS; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 479b654d54..2b42de60b1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ typedef struct { } RISCVSATPMap; struct RISCVCPUConfig { - bool ext_e; bool ext_g; bool ext_m; bool ext_s; diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index d75acbc4a6..a727169a4b 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -117,7 +117,7 @@ static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist) { uint32_t reg_bitmap = 0; - if (ctx->cfg_ptr->ext_e && rlist > 6) { + if (has_ext(ctx, RVE) && rlist > 6) { return 0; } -- 2.11.4.GIT