target/riscv: Add support for Zce
commit00d312bd78c91650e05b6e9676650db6865576f0
authorWeiwei Li <liweiwei@iscas.ac.cn>
Tue, 7 Mar 2023 08:14:03 +0000 (7 16:14 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 5 May 2023 00:49:50 +0000 (5 10:49 +1000)
treed8f82ae20d6d12bc94ff075217d8137d29b01317
parent2c71d02e17771f58ce4d89ca71b756fb3ecf9525
target/riscv: Add support for Zce

Add and expose property for Zce:
* Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt.
* Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h