target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "hw/registerfields.h"
  25 #include "exec/cpu-defs.h"
  26 #include "qemu/cpu-float.h"
  27 #include "qom/object.h"
  28 #include "qemu/int128.h"
  29 #include "cpu_bits.h"
  30 #include "qapi/qapi-types-common.h"
  31
  32 #define TCG_GUEST_DEFAULT_MO 0
  33
  34 /*
  35  * RISC-V-specific extra insn start words:
  36  * 1: Original instruction opcode
  37  */
  38 #define TARGET_INSN_START_EXTRA_WORDS 1
  39
  40 #define TYPE_RISCV_CPU "riscv-cpu"
  41
  42 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  43 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  44 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  45
  46 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  47 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  48 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  49 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
  50 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
  51 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
  52 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  53 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  54 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  55 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  56 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  57 #define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
  58 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
  59
  60 #if defined(TARGET_RISCV32)
  61 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  62 #elif defined(TARGET_RISCV64)
  63 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  64 #endif
  65
  66 #define RV(x) ((target_ulong)1 << (x - 'A'))
  67
  68 /*
  69  * Consider updating register_cpu_props() when adding
  70  * new MISA bits here.
  71  */
  72 #define RVI RV('I')
  73 #define RVE RV('E') /* E and I are mutually exclusive */
  74 #define RVM RV('M')
  75 #define RVA RV('A')
  76 #define RVF RV('F')
  77 #define RVD RV('D')
  78 #define RVV RV('V')
  79 #define RVC RV('C')
  80 #define RVS RV('S')
  81 #define RVU RV('U')
  82 #define RVH RV('H')
  83 #define RVJ RV('J')
  84
  85
  86 /* Privileged specification version */
  87 enum {
  88     PRIV_VERSION_1_10_0 = 0,
  89     PRIV_VERSION_1_11_0,
  90     PRIV_VERSION_1_12_0,
  91 };
  92
  93 #define VEXT_VERSION_1_00_0 0x00010000
  94
  95 enum {
  96     TRANSLATE_SUCCESS,
  97     TRANSLATE_FAIL,
  98     TRANSLATE_PMP_FAIL,
  99     TRANSLATE_G_STAGE_FAIL
 100 };
 101
 102 #define MMU_USER_IDX 3
 103
 104 #define MAX_RISCV_PMPS (16)
 105
 106 typedef struct CPUArchState CPURISCVState;
 107
 108 #if !defined(CONFIG_USER_ONLY)
 109 #include "pmp.h"
 110 #include "debug.h"
 111 #endif
 112
 113 #define RV_VLEN_MAX 1024
 114 #define RV_MAX_MHPMEVENTS 32
 115 #define RV_MAX_MHPMCOUNTERS 32
 116
 117 FIELD(VTYPE, VLMUL, 0, 3)
 118 FIELD(VTYPE, VSEW, 3, 3)
 119 FIELD(VTYPE, VTA, 6, 1)
 120 FIELD(VTYPE, VMA, 7, 1)
 121 FIELD(VTYPE, VEDIV, 8, 2)
 122 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 123
 124 typedef struct PMUCTRState {
 125     /* Current value of a counter */
 126     target_ulong mhpmcounter_val;
 127     /* Current value of a counter in RV32*/
 128     target_ulong mhpmcounterh_val;
 129     /* Snapshot values of counter */
 130     target_ulong mhpmcounter_prev;
 131     /* Snapshort value of a counter in RV32 */
 132     target_ulong mhpmcounterh_prev;
 133     bool started;
 134     /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */
 135     target_ulong irq_overflow_left;
 136 } PMUCTRState;
 137
 138 struct CPUArchState {
 139     target_ulong gpr[32];
 140     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
 141
 142     /* vector coprocessor state. */
 143     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
 144     target_ulong vxrm;
 145     target_ulong vxsat;
 146     target_ulong vl;
 147     target_ulong vstart;
 148     target_ulong vtype;
 149     bool vill;
 150
 151     target_ulong pc;
 152     target_ulong load_res;
 153     target_ulong load_val;
 154
 155     /* Floating-Point state */
 156     uint64_t fpr[32]; /* assume both F and D extensions */
 157     target_ulong frm;
 158     float_status fp_status;
 159
 160     target_ulong badaddr;
 161     target_ulong bins;
 162
 163     target_ulong guest_phys_fault_addr;
 164
 165     target_ulong priv_ver;
 166     target_ulong bext_ver;
 167     target_ulong vext_ver;
 168
 169     /* RISCVMXL, but uint32_t for vmstate migration */
 170     uint32_t misa_mxl;      /* current mxl */
 171     uint32_t misa_mxl_max;  /* max mxl for this cpu */
 172     uint32_t misa_ext;      /* current extensions */
 173     uint32_t misa_ext_mask; /* max ext for this cpu */
 174     uint32_t xl;            /* current xlen */
 175
 176     /* 128-bit helpers upper part return value */
 177     target_ulong retxh;
 178
 179     target_ulong jvt;
 180
 181 #ifdef CONFIG_USER_ONLY
 182     uint32_t elf_flags;
 183 #endif
 184
 185 #ifndef CONFIG_USER_ONLY
 186     target_ulong priv;
 187     /* This contains QEMU specific information about the virt state. */
 188     target_ulong virt;
 189     target_ulong geilen;
 190     uint64_t resetvec;
 191
 192     target_ulong mhartid;
 193     /*
 194      * For RV32 this is 32-bit mstatus and 32-bit mstatush.
 195      * For RV64 this is a 64-bit mstatus.
 196      */
 197     uint64_t mstatus;
 198
 199     uint64_t mip;
 200     /*
 201      * MIP contains the software writable version of SEIP ORed with the
 202      * external interrupt value. The MIP register is always up-to-date.
 203      * To keep track of the current source, we also save booleans of the values
 204      * here.
 205      */
 206     bool external_seip;
 207     bool software_seip;
 208
 209     uint64_t miclaim;
 210
 211     uint64_t mie;
 212     uint64_t mideleg;
 213
 214     target_ulong satp;   /* since: priv-1.10.0 */
 215     target_ulong stval;
 216     target_ulong medeleg;
 217
 218     target_ulong stvec;
 219     target_ulong sepc;
 220     target_ulong scause;
 221
 222     target_ulong mtvec;
 223     target_ulong mepc;
 224     target_ulong mcause;
 225     target_ulong mtval;  /* since: priv-1.10.0 */
 226
 227     /* Machine and Supervisor interrupt priorities */
 228     uint8_t miprio[64];
 229     uint8_t siprio[64];
 230
 231     /* AIA CSRs */
 232     target_ulong miselect;
 233     target_ulong siselect;
 234
 235     /* Hypervisor CSRs */
 236     target_ulong hstatus;
 237     target_ulong hedeleg;
 238     uint64_t hideleg;
 239     target_ulong hcounteren;
 240     target_ulong htval;
 241     target_ulong htinst;
 242     target_ulong hgatp;
 243     target_ulong hgeie;
 244     target_ulong hgeip;
 245     uint64_t htimedelta;
 246
 247     /* Hypervisor controlled virtual interrupt priorities */
 248     target_ulong hvictl;
 249     uint8_t hviprio[64];
 250
 251     /* Upper 64-bits of 128-bit CSRs */
 252     uint64_t mscratchh;
 253     uint64_t sscratchh;
 254
 255     /* Virtual CSRs */
 256     /*
 257      * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
 258      * For RV64 this is a 64-bit vsstatus.
 259      */
 260     uint64_t vsstatus;
 261     target_ulong vstvec;
 262     target_ulong vsscratch;
 263     target_ulong vsepc;
 264     target_ulong vscause;
 265     target_ulong vstval;
 266     target_ulong vsatp;
 267
 268     /* AIA VS-mode CSRs */
 269     target_ulong vsiselect;
 270
 271     target_ulong mtval2;
 272     target_ulong mtinst;
 273
 274     /* HS Backup CSRs */
 275     target_ulong stvec_hs;
 276     target_ulong sscratch_hs;
 277     target_ulong sepc_hs;
 278     target_ulong scause_hs;
 279     target_ulong stval_hs;
 280     target_ulong satp_hs;
 281     uint64_t mstatus_hs;
 282
 283     /* Signals whether the current exception occurred with two-stage address
 284        translation active. */
 285     bool two_stage_lookup;
 286     /*
 287      * Signals whether the current exception occurred while doing two-stage
 288      * address translation for the VS-stage page table walk.
 289      */
 290     bool two_stage_indirect_lookup;
 291
 292     target_ulong scounteren;
 293     target_ulong mcounteren;
 294
 295     target_ulong mcountinhibit;
 296
 297     /* PMU counter state */
 298     PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
 299
 300     /* PMU event selector configured values. First three are unused*/
 301     target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
 302
 303     /* PMU event selector configured values for RV32*/
 304     target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
 305
 306     target_ulong sscratch;
 307     target_ulong mscratch;
 308
 309     /* Sstc CSRs */
 310     uint64_t stimecmp;
 311
 312     uint64_t vstimecmp;
 313
 314     /* physical memory protection */
 315     pmp_table_t pmp_state;
 316     target_ulong mseccfg;
 317
 318     /* trigger module */
 319     target_ulong trigger_cur;
 320     target_ulong tdata1[RV_MAX_TRIGGERS];
 321     target_ulong tdata2[RV_MAX_TRIGGERS];
 322     target_ulong tdata3[RV_MAX_TRIGGERS];
 323     struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
 324     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
 325     QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
 326     int64_t last_icount;
 327     bool itrigger_enabled;
 328
 329     /* machine specific rdtime callback */
 330     uint64_t (*rdtime_fn)(void *);
 331     void *rdtime_fn_arg;
 332
 333     /* machine specific AIA ireg read-modify-write callback */
 334 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
 335     ((((__xlen) & 0xff) << 24) | \
 336      (((__vgein) & 0x3f) << 20) | \
 337      (((__virt) & 0x1) << 18) | \
 338      (((__priv) & 0x3) << 16) | \
 339      (__isel & 0xffff))
 340 #define AIA_IREG_ISEL(__ireg)                  ((__ireg) & 0xffff)
 341 #define AIA_IREG_PRIV(__ireg)                  (((__ireg) >> 16) & 0x3)
 342 #define AIA_IREG_VIRT(__ireg)                  (((__ireg) >> 18) & 0x1)
 343 #define AIA_IREG_VGEIN(__ireg)                 (((__ireg) >> 20) & 0x3f)
 344 #define AIA_IREG_XLEN(__ireg)                  (((__ireg) >> 24) & 0xff)
 345     int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
 346         target_ulong *val, target_ulong new_val, target_ulong write_mask);
 347     void *aia_ireg_rmw_fn_arg[4];
 348
 349     /* True if in debugger mode.  */
 350     bool debugger;
 351
 352     /*
 353      * CSRs for PointerMasking extension
 354      */
 355     target_ulong mmte;
 356     target_ulong mpmmask;
 357     target_ulong mpmbase;
 358     target_ulong spmmask;
 359     target_ulong spmbase;
 360     target_ulong upmmask;
 361     target_ulong upmbase;
 362
 363     /* CSRs for execution enviornment configuration */
 364     uint64_t menvcfg;
 365     uint64_t mstateen[SMSTATEEN_MAX_COUNT];
 366     uint64_t hstateen[SMSTATEEN_MAX_COUNT];
 367     uint64_t sstateen[SMSTATEEN_MAX_COUNT];
 368     target_ulong senvcfg;
 369     uint64_t henvcfg;
 370 #endif
 371     target_ulong cur_pmmask;
 372     target_ulong cur_pmbase;
 373
 374     /* Fields from here on are preserved across CPU reset. */
 375     QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
 376     QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
 377     bool vstime_irq;
 378
 379     hwaddr kernel_addr;
 380     hwaddr fdt_addr;
 381
 382     /* kvm timer */
 383     bool kvm_timer_dirty;
 384     uint64_t kvm_timer_time;
 385     uint64_t kvm_timer_compare;
 386     uint64_t kvm_timer_state;
 387     uint64_t kvm_timer_frequency;
 388 };
 389
 390 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 391
 392 /**
 393  * RISCVCPUClass:
 394  * @parent_realize: The parent class' realize handler.
 395  * @parent_phases: The parent class' reset phase handlers.
 396  *
 397  * A RISCV CPU model.
 398  */
 399 struct RISCVCPUClass {
 400     /*< private >*/
 401     CPUClass parent_class;
 402     /*< public >*/
 403     DeviceRealize parent_realize;
 404     ResettablePhases parent_phases;
 405 };
 406
 407 /*
 408  * map is a 16-bit bitmap: the most significant set bit in map is the maximum
 409  * satp mode that is supported. It may be chosen by the user and must respect
 410  * what qemu implements (valid_1_10_32/64) and what the hw is capable of
 411  * (supported bitmap below).
 412  *
 413  * init is a 16-bit bitmap used to make sure the user selected a correct
 414  * configuration as per the specification.
 415  *
 416  * supported is a 16-bit bitmap used to reflect the hw capabilities.
 417  */
 418 typedef struct {
 419     uint16_t map, init, supported;
 420 } RISCVSATPMap;
 421
 422 struct RISCVCPUConfig {
 423     bool ext_i;
 424     bool ext_e;
 425     bool ext_g;
 426     bool ext_m;
 427     bool ext_a;
 428     bool ext_f;
 429     bool ext_d;
 430     bool ext_c;
 431     bool ext_s;
 432     bool ext_u;
 433     bool ext_h;
 434     bool ext_j;
 435     bool ext_v;
 436     bool ext_zba;
 437     bool ext_zbb;
 438     bool ext_zbc;
 439     bool ext_zbkb;
 440     bool ext_zbkc;
 441     bool ext_zbkx;
 442     bool ext_zbs;
 443     bool ext_zca;
 444     bool ext_zcb;
 445     bool ext_zcd;
 446     bool ext_zce;
 447     bool ext_zcf;
 448     bool ext_zcmp;
 449     bool ext_zcmt;
 450     bool ext_zk;
 451     bool ext_zkn;
 452     bool ext_zknd;
 453     bool ext_zkne;
 454     bool ext_zknh;
 455     bool ext_zkr;
 456     bool ext_zks;
 457     bool ext_zksed;
 458     bool ext_zksh;
 459     bool ext_zkt;
 460     bool ext_ifencei;
 461     bool ext_icsr;
 462     bool ext_icbom;
 463     bool ext_icboz;
 464     bool ext_zicond;
 465     bool ext_zihintpause;
 466     bool ext_smstateen;
 467     bool ext_sstc;
 468     bool ext_svadu;
 469     bool ext_svinval;
 470     bool ext_svnapot;
 471     bool ext_svpbmt;
 472     bool ext_zdinx;
 473     bool ext_zawrs;
 474     bool ext_zfh;
 475     bool ext_zfhmin;
 476     bool ext_zfinx;
 477     bool ext_zhinx;
 478     bool ext_zhinxmin;
 479     bool ext_zve32f;
 480     bool ext_zve64f;
 481     bool ext_zve64d;
 482     bool ext_zmmul;
 483     bool ext_zvfh;
 484     bool ext_zvfhmin;
 485     bool ext_smaia;
 486     bool ext_ssaia;
 487     bool ext_sscofpmf;
 488     bool rvv_ta_all_1s;
 489     bool rvv_ma_all_1s;
 490
 491     uint32_t mvendorid;
 492     uint64_t marchid;
 493     uint64_t mimpid;
 494
 495     /* Vendor-specific custom extensions */
 496     bool ext_xtheadba;
 497     bool ext_xtheadbb;
 498     bool ext_xtheadbs;
 499     bool ext_xtheadcmo;
 500     bool ext_xtheadcondmov;
 501     bool ext_xtheadfmemidx;
 502     bool ext_xtheadfmv;
 503     bool ext_xtheadmac;
 504     bool ext_xtheadmemidx;
 505     bool ext_xtheadmempair;
 506     bool ext_xtheadsync;
 507     bool ext_XVentanaCondOps;
 508
 509     uint8_t pmu_num;
 510     char *priv_spec;
 511     char *user_spec;
 512     char *bext_spec;
 513     char *vext_spec;
 514     uint16_t vlen;
 515     uint16_t elen;
 516     uint16_t cbom_blocksize;
 517     uint16_t cboz_blocksize;
 518     bool mmu;
 519     bool pmp;
 520     bool epmp;
 521     bool debug;
 522     bool misa_w;
 523
 524     bool short_isa_string;
 525
 526 #ifndef CONFIG_USER_ONLY
 527     RISCVSATPMap satp_mode;
 528 #endif
 529 };
 530
 531 typedef struct RISCVCPUConfig RISCVCPUConfig;
 532
 533 /**
 534  * RISCVCPU:
 535  * @env: #CPURISCVState
 536  *
 537  * A RISCV CPU.
 538  */
 539 struct ArchCPU {
 540     /*< private >*/
 541     CPUState parent_obj;
 542     /*< public >*/
 543     CPUNegativeOffsetState neg;
 544     CPURISCVState env;
 545
 546     char *dyn_csr_xml;
 547     char *dyn_vreg_xml;
 548
 549     /* Configuration Settings */
 550     RISCVCPUConfig cfg;
 551
 552     QEMUTimer *pmu_timer;
 553     /* A bitmask of Available programmable counters */
 554     uint32_t pmu_avail_ctrs;
 555     /* Mapping of events to counters */
 556     GHashTable *pmu_event_ctr_map;
 557 };
 558
 559 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 560 {
 561     return (env->misa_ext & ext) != 0;
 562 }
 563
 564 #include "cpu_user.h"
 565
 566 extern const char * const riscv_int_regnames[];
 567 extern const char * const riscv_int_regnamesh[];
 568 extern const char * const riscv_fpr_regnames[];
 569
 570 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 571 void riscv_cpu_do_interrupt(CPUState *cpu);
 572 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 573                                int cpuid, DumpState *s);
 574 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
 575                                int cpuid, DumpState *s);
 576 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 577 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 578 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 579 uint8_t riscv_cpu_default_priority(int irq);
 580 uint64_t riscv_cpu_all_pending(CPURISCVState *env);
 581 int riscv_cpu_mirq_pending(CPURISCVState *env);
 582 int riscv_cpu_sirq_pending(CPURISCVState *env);
 583 int riscv_cpu_vsirq_pending(CPURISCVState *env);
 584 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 585 target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
 586 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
 587 bool riscv_cpu_vector_enabled(CPURISCVState *env);
 588 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 589 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 590 bool riscv_cpu_two_stage_lookup(int mmu_idx);
 591 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 592 G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 593                                                MMUAccessType access_type, int mmu_idx,
 594                                                uintptr_t retaddr);
 595 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 596                         MMUAccessType access_type, int mmu_idx,
 597                         bool probe, uintptr_t retaddr);
 598 char *riscv_isa_string(RISCVCPU *cpu);
 599 void riscv_cpu_list(void);
 600
 601 #define cpu_list riscv_cpu_list
 602 #define cpu_mmu_index riscv_cpu_mmu_index
 603
 604 #ifndef CONFIG_USER_ONLY
 605 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 606                                      vaddr addr, unsigned size,
 607                                      MMUAccessType access_type,
 608                                      int mmu_idx, MemTxAttrs attrs,
 609                                      MemTxResult response, uintptr_t retaddr);
 610 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 611 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 612 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 613 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
 614 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
 615                               uint64_t value);
 616 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 617 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
 618                              void *arg);
 619 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
 620                                    int (*rmw_fn)(void *arg,
 621                                                  target_ulong reg,
 622                                                  target_ulong *val,
 623                                                  target_ulong new_val,
 624                                                  target_ulong write_mask),
 625                                    void *rmw_fn_arg);
 626
 627 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
 628 #endif
 629 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 630
 631 void riscv_translate_init(void);
 632 G_NORETURN void riscv_raise_exception(CPURISCVState *env,
 633                                       uint32_t exception, uintptr_t pc);
 634
 635 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 636 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 637
 638 #define TB_FLAGS_PRIV_MMU_MASK                3
 639 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 640 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 641 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 642
 643 #include "exec/cpu-all.h"
 644
 645 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 646 FIELD(TB_FLAGS, LMUL, 3, 3)
 647 FIELD(TB_FLAGS, SEW, 6, 3)
 648 /* Skip MSTATUS_VS (0x600) bits */
 649 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
 650 FIELD(TB_FLAGS, VILL, 12, 1)
 651 /* Skip MSTATUS_FS (0x6000) bits */
 652 /* Is a Hypervisor instruction load/store allowed? */
 653 FIELD(TB_FLAGS, HLSX, 15, 1)
 654 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
 655 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 656 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
 657 FIELD(TB_FLAGS, XL, 20, 2)
 658 /* If PointerMasking should be applied */
 659 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
 660 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
 661 FIELD(TB_FLAGS, VTA, 24, 1)
 662 FIELD(TB_FLAGS, VMA, 25, 1)
 663 /* Native debug itrigger */
 664 FIELD(TB_FLAGS, ITRIGGER, 26, 1)
 665
 666 #ifdef TARGET_RISCV32
 667 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 668 #else
 669 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 670 {
 671     return env->misa_mxl;
 672 }
 673 #endif
 674 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 675
 676 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
 677 {
 678     return &env_archcpu(env)->cfg;
 679 }
 680
 681 #if defined(TARGET_RISCV32)
 682 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 683 #else
 684 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 685 {
 686     RISCVMXL xl = env->misa_mxl;
 687 #if !defined(CONFIG_USER_ONLY)
 688     /*
 689      * When emulating a 32-bit-only cpu, use RV32.
 690      * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 691      * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 692      * back to RV64 for lower privs.
 693      */
 694     if (xl != MXL_RV32) {
 695         switch (env->priv) {
 696         case PRV_M:
 697             break;
 698         case PRV_U:
 699             xl = get_field(env->mstatus, MSTATUS64_UXL);
 700             break;
 701         default: /* PRV_S | PRV_H */
 702             xl = get_field(env->mstatus, MSTATUS64_SXL);
 703             break;
 704         }
 705     }
 706 #endif
 707     return xl;
 708 }
 709 #endif
 710
 711 static inline int riscv_cpu_xlen(CPURISCVState *env)
 712 {
 713     return 16 << env->xl;
 714 }
 715
 716 #ifdef TARGET_RISCV32
 717 #define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
 718 #else
 719 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
 720 {
 721 #ifdef CONFIG_USER_ONLY
 722     return env->misa_mxl;
 723 #else
 724     return get_field(env->mstatus, MSTATUS64_SXL);
 725 #endif
 726 }
 727 #endif
 728
 729 /*
 730  * Encode LMUL to lmul as follows:
 731  *     LMUL    vlmul    lmul
 732  *      1       000       0
 733  *      2       001       1
 734  *      4       010       2
 735  *      8       011       3
 736  *      -       100       -
 737  *     1/8      101      -3
 738  *     1/4      110      -2
 739  *     1/2      111      -1
 740  *
 741  * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
 742  * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
 743  *      => VLMAX = vlen >> (1 + 3 - (-3))
 744  *               = 256 >> 7
 745  *               = 2
 746  */
 747 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 748 {
 749     uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
 750     int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
 751     return cpu->cfg.vlen >> (sew + 3 - lmul);
 752 }
 753
 754 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 755                           target_ulong *cs_base, uint32_t *pflags);
 756
 757 void riscv_cpu_update_mask(CPURISCVState *env);
 758
 759 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
 760                            target_ulong *ret_value,
 761                            target_ulong new_value, target_ulong write_mask);
 762 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
 763                                  target_ulong *ret_value,
 764                                  target_ulong new_value,
 765                                  target_ulong write_mask);
 766
 767 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 768                                    target_ulong val)
 769 {
 770     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 771 }
 772
 773 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 774 {
 775     target_ulong val = 0;
 776     riscv_csrrw(env, csrno, &val, 0, 0);
 777     return val;
 778 }
 779
 780 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
 781                                                  int csrno);
 782 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 783                                             target_ulong *ret_value);
 784 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 785                                              target_ulong new_value);
 786 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 787                                           target_ulong *ret_value,
 788                                           target_ulong new_value,
 789                                           target_ulong write_mask);
 790
 791 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
 792                                 Int128 *ret_value,
 793                                 Int128 new_value, Int128 write_mask);
 794
 795 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
 796                                                Int128 *ret_value);
 797 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
 798                                              Int128 new_value);
 799
 800 typedef struct {
 801     const char *name;
 802     riscv_csr_predicate_fn predicate;
 803     riscv_csr_read_fn read;
 804     riscv_csr_write_fn write;
 805     riscv_csr_op_fn op;
 806     riscv_csr_read128_fn read128;
 807     riscv_csr_write128_fn write128;
 808     /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
 809     uint32_t min_priv_ver;
 810 } riscv_csr_operations;
 811
 812 /* CSR function table constants */
 813 enum {
 814     CSR_TABLE_SIZE = 0x1000
 815 };
 816
 817 /**
 818  * The event id are encoded based on the encoding specified in the
 819  * SBI specification v0.3
 820  */
 821
 822 enum riscv_pmu_event_idx {
 823     RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,
 824     RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,
 825     RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,
 826     RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,
 827     RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
 828 };
 829
 830 /* CSR function table */
 831 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
 832
 833 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
 834
 835 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 836 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 837
 838 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 839
 840 uint8_t satp_mode_max_from_map(uint32_t map);
 841 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 842
 843 #endif /* RISCV_CPU_H */