| commit | b84ffd6e74b5e4e7ddbb492bc9c8d798c8261703 | |
| author | Weiwei Li <liweiwei@iscas.ac.cn> | |
| Wed, 17 May 2023 09:15:12 +0000 (17 17:15 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 13 Jun 2023 07:10:02 +0000 (13 17:10 +1000) | ||
| tree | df51d10bd05af428db7e21ca0a89af183e239ed6 | treesnapshot (tar.gz zip) |
| parent | e9c39713ea09faa74f502e32d71d52c1c2e8ccf1 | commitdiff |
target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
So they can only be writable and set to 1s when cfg.epmp is true.
Then we also need't check on epmp in pmp_hart_has_privs_default().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
So they can only be writable and set to 1s when cfg.epmp is true.
Then we also need't check on epmp in pmp_hart_has_privs_default().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/pmp.c | diffblobblamehistory |