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target/riscv: Use gen_unary_per_ol for RVB
2021-10-22 Richard Hendersontarget/riscv: Use gen_unary_per_ol for RVB
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Richard Hendersontarget/riscv: Adjust trans_rev8_32 for riscv64
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Richard Hendersontarget/riscv: Use gen_arith_per_ol for RVM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Replace DisasContext.w with DisasContext.ol
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Replace is_32bit with get_xl/get_xlen
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Properly check SEW in amo_op
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Use REQUIRE_64BIT in amo_check64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Add MXL/SXL/UXL to TB_FLAGS
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Split misa.mxl and misa.ext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Create RISCVMXL enumeration
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Move cpu_get_tb_cpu_state out of line
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Alistair Francistarget/riscv: Organise the CPU properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Alistair Francistarget/riscv: Remove some unused macros
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2021-10-21 Frank Changtarget/riscv: fix TB_FLAGS bits overlapping bug for...
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2021-10-21 Mingwang Lihw/riscv: virt: Use machine->ram as the system memory
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Philipp Tomsichtarget/riscv: Fix orc.b implementation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Travis Geiselbrechttarget/riscv: line up all of the registers in the info...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Frank Changtarget/riscv: Pass the same value to oprsz and maxsz...
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2021-10-06 Alistair Francishw/riscv: shakti_c: Mark as not user creatable
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2021-10-06 Bin Menghw/dma: sifive_pdma: Don't run DMA when channel is...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/dma: sifive_pdma: Fix Control.claim bit detection
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/char: sifive_uart: Register device in 'input' category
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/char: shakti_uart: Register device in 'input' category
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/char: ibex_uart: Register device in 'input' category
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Frank Changtarget/riscv: Set mstatus_hs.[SD|FS] bits if Clean...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichdisas/riscv: Add Zb[abcs] instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Remove RVB (replaced by Zb[abcs])
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add zext.h instructions to Zbb, removing...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add rev8 instruction, removing grev/grevi
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add a REQUIRE_32BIT macro
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add orc.b instruction for Zbb, removing...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbb-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add instructions of the Zbc-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbs-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Remove shift-one instructions (proposed...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Remove the W-form instructions from Zbs
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zba-extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: clwz must ignore high bits (use shift...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: fix clzw implementation to operate on...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Introduce temporary in gen_add_uw()
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Alistair Francishw/riscv: opentitan: Correct the USB Dev address
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Bin Mengtarget/riscv: csr: Rename HCOUNTEREN_CY and friends
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Frank Changtarget/riscv: Backup/restore mstatus.SD bit when virtual...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Bin Mengdocs/system/riscv: sifive_u: Update U-Boot instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: don't set Control.error if 0 bytes...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Green Wanhw/dma: sifive_pdma: allow non-multiple transaction...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: claim bit must be set before DMA...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: reset Next* registers when Control...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Add optional ACLINT support to virt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Re-factor FDT generation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Upgrade the SiFive CLINT implementation to...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Rename sifive_clint sources to riscv_aclint...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francissifive_u: Connect the SiFive PWM device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/timer: Add SiFive PWM support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_timer: Convert the timer to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_plic: Convert the PLIC to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_plic: Convert the PLIC to use RISC-V...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Expose interrupt pending bits as GPIO...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 LIU Zhiweitarget/riscv: Fix satp write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Update the ePMP CSR address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVV
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Tidy trans_rvh.c.inc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVD
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVF
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use gen_shift_imm_fn for slli_uw
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get,dest}_gpr for RVA
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Reorg csr instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Fix hgeie, hgeip
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use {get, dest}_gpr for integer load...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use get_gpr in branches
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use extracts for sraiw and srliw
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use DisasExtend in shift operations
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Add DisasExtend to gen_unary
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Move gen_* helpers for RVB
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Move gen_* helpers for RVM
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Use gen_arith for mulh and mulhu
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Remove gen_arith_div*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Add DisasExtend to gen_arith*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Introduce DisasExtend and new helpers
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontarget/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
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2021-09-01 Richard Hendersontarget/riscv: Clean up division helpers
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Richard Hendersontests/tcg/riscv64: Add test for division
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2021-09-01 Richard Hendersontarget/riscv: Use tcg_constant_*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Joe Komlodihw/registerfields: Use 64-bit bitfield for FIELD_DP64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Joe Komlodihw/core/register: Add more 64-bit utilities
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 David Hoppenbrouwershw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Peter Maydellhw/riscv/virt.c: Assemble plic_hart_config string with...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 LIU Zhiweitarget/riscv: Add User CSRs read-only check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 LIU Zhiweitarget/riscv: Don't wrongly override isa version
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Mengtarget/riscv: Correct a comment in riscv_csrrw()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Bin Menghw/riscv: virt: Move flash node to root
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-01 Vijai Kumar Khw/char: Add config for shakti uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv/boot: Check the error of fdt_pack()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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