| commit | e573a7f325e4d66d1005f7bb80d51ce95f307951 | |
| author | Travis Geiselbrecht <travisg@gmail.com> | |
| Sat, 9 Oct 2021 05:50:19 +0000 (8 22:50 -0700) | ||
| committer | Alistair Francis <alistair@alistair23.me> | |
| Thu, 21 Oct 2021 21:47:51 +0000 (22 07:47 +1000) | ||
| tree | 7652bc25f5ee55818fd2f74a49513bcb04f58459 | treesnapshot (tar.gz zip) |
| parent | c672f19f328922eff4963b0b61fbdcfa661e1c06 | commitdiff |
target/riscv: line up all of the registers in the info register dump
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory |