target/riscv: Properly check SEW in amo_op
commit4e97d459a0f2b92815c2c2c6eb96b75e2235b42e
authorRichard Henderson <richard.henderson@linaro.org>
Wed, 20 Oct 2021 03:17:01 +0000 (19 20:17 -0700)
committerAlistair Francis <alistair@alistair23.me>
Thu, 21 Oct 2021 21:47:51 +0000 (22 07:47 +1000)
tree7d34d475c80cee99fb6fd111bf95d4b931004dfe
parentfbb48032e46976cfc94a90a4233a2060fdc36a4e
target/riscv: Properly check SEW in amo_op

We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less.  Use a switch and explicitly
bound both SEW and SEQ for all cases.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-8-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc