target/riscv: Add DisasExtend to gen_arith*
commit191d1dafae9cd502ef2d771f9e35c221815fe7ba
authorRichard Henderson <richard.henderson@linaro.org>
Mon, 23 Aug 2021 19:55:11 +0000 (23 12:55 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 1 Sep 2021 01:59:12 +0000 (1 11:59 +1000)
tree73be9fde020f83a1316ddcf3ddc59a5858ff2329
parentecda15d137457ebed937dc209f4bad2e7f36b4e4
target/riscv: Add DisasExtend to gen_arith*

Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.

Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-7-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvb.c.inc
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/insn_trans/trans_rvm.c.inc
target/riscv/translate.c