| commit | 57a3a6226529e60ef4eb5e11b577f2e532a72acc | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Mon, 30 Aug 2021 05:35:15 +0000 (30 15:35 +1000) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Mon, 20 Sep 2021 21:56:49 +0000 (21 07:56 +1000) | ||
| tree | 26b5f8a9f08a1ea63b22635e2a0c44e0414293f4 | treesnapshot (tar.gz zip) |
| parent | f436ecc3156dea7edce97e7c247e3667203f5c8b | commitdiff |
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
| hw/riscv/opentitan.c | diffblobblamehistory | |
| hw/timer/ibex_timer.c | diffblobblamehistory | |
| include/hw/timer/ibex_timer.h | diffblobblamehistory |