target/riscv: Split misa.mxl and misa.ext
commite91a7227cb802ea62ffa14707ebc2f588b01213d
authorRichard Henderson <richard.henderson@linaro.org>
Wed, 20 Oct 2021 03:16:57 +0000 (19 20:16 -0700)
committerAlistair Francis <alistair@alistair23.me>
Thu, 21 Oct 2021 21:47:51 +0000 (22 07:47 +1000)
tree83e6aa01014f64717ecdcf2b0b7ee2b42ef44b72
parent99bc874fb3a0709c36ae4e594a1262ce1660e698
target/riscv: Split misa.mxl and misa.ext

The hw representation of misa.mxl is at the high bits of the
misa csr.  Representing this in the same way inside QEMU
results in overly complex code trying to check that field.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
linux-user/elfload.c
linux-user/riscv/cpu_loop.c
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/csr.c
target/riscv/gdbstub.c
target/riscv/machine.c
target/riscv/translate.c