target/riscv/translate.c

   1 /*
   2  * RISC-V emulation for qemu: main translation routines.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "cpu.h"
  22 #include "tcg/tcg-op.h"
  23 #include "disas/disas.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/helper-proto.h"
  27 #include "exec/helper-gen.h"
  28
  29 #include "exec/translator.h"
  30 #include "exec/log.h"
  31
  32 #include "instmap.h"
  33
  34 /* global register indices */
  35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
  36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
  37 static TCGv load_res;
  38 static TCGv load_val;
  39
  40 #include "exec/gen-icount.h"
  41
  42 /*
  43  * If an operation is being performed on less than TARGET_LONG_BITS,
  44  * it may require the inputs to be sign- or zero-extended; which will
  45  * depend on the exact operation being performed.
  46  */
  47 typedef enum {
  48     EXT_NONE,
  49     EXT_SIGN,
  50     EXT_ZERO,
  51 } DisasExtend;
  52
  53 typedef struct DisasContext {
  54     DisasContextBase base;
  55     /* pc_succ_insn points to the instruction following base.pc_next */
  56     target_ulong pc_succ_insn;
  57     target_ulong priv_ver;
  58     RISCVMXL xl;
  59     uint32_t misa_ext;
  60     uint32_t opcode;
  61     uint32_t mstatus_fs;
  62     uint32_t mstatus_hs_fs;
  63     uint32_t mem_idx;
  64     /* Remember the rounding mode encoded in the previous fp instruction,
  65        which we have already installed into env->fp_status.  Or -1 for
  66        no previous fp instruction.  Note that we exit the TB when writing
  67        to any system register, which includes CSR_FRM, so we do not have
  68        to reset this known value.  */
  69     int frm;
  70     bool w;
  71     bool virt_enabled;
  72     bool ext_ifencei;
  73     bool hlsx;
  74     /* vector extension */
  75     bool vill;
  76     uint8_t lmul;
  77     uint8_t sew;
  78     uint16_t vlen;
  79     uint16_t mlen;
  80     bool vl_eq_vlmax;
  81     uint8_t ntemp;
  82     CPUState *cs;
  83     TCGv zero;
  84     /* Space for 3 operands plus 1 extra for address computation. */
  85     TCGv temp[4];
  86 } DisasContext;
  87
  88 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  89 {
  90     return ctx->misa_ext & ext;
  91 }
  92
  93 #ifdef TARGET_RISCV32
  94 # define is_32bit(ctx)  true
  95 #elif defined(CONFIG_USER_ONLY)
  96 # define is_32bit(ctx)  false
  97 #else
  98 static inline bool is_32bit(DisasContext *ctx)
  99 {
 100     return ctx->xl == MXL_RV32;
 101 }
 102 #endif
 103
 104 /* The word size for this operation. */
 105 static inline int oper_len(DisasContext *ctx)
 106 {
 107     return ctx->w ? 32 : TARGET_LONG_BITS;
 108 }
 109
 110
 111 /*
 112  * RISC-V requires NaN-boxing of narrower width floating point values.
 113  * This applies when a 32-bit value is assigned to a 64-bit FP register.
 114  * For consistency and simplicity, we nanbox results even when the RVD
 115  * extension is not present.
 116  */
 117 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 118 {
 119     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
 120 }
 121
 122 /*
 123  * A narrow n-bit operation, where n < FLEN, checks that input operands
 124  * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
 125  * If so, the least-significant bits of the input are used, otherwise the
 126  * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
 127  *
 128  * Here, the result is always nan-boxed, even the canonical nan.
 129  */
 130 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 131 {
 132     TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
 133     TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
 134
 135     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 136 }
 137
 138 static void generate_exception(DisasContext *ctx, int excp)
 139 {
 140     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 141     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
 142     ctx->base.is_jmp = DISAS_NORETURN;
 143 }
 144
 145 static void generate_exception_mtval(DisasContext *ctx, int excp)
 146 {
 147     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 148     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 149     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
 150     ctx->base.is_jmp = DISAS_NORETURN;
 151 }
 152
 153 static void gen_exception_illegal(DisasContext *ctx)
 154 {
 155     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 156 }
 157
 158 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 159 {
 160     generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
 161 }
 162
 163 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 164 {
 165     if (translator_use_goto_tb(&ctx->base, dest)) {
 166         tcg_gen_goto_tb(n);
 167         tcg_gen_movi_tl(cpu_pc, dest);
 168         tcg_gen_exit_tb(ctx->base.tb, n);
 169     } else {
 170         tcg_gen_movi_tl(cpu_pc, dest);
 171         tcg_gen_lookup_and_goto_ptr();
 172     }
 173 }
 174
 175 /*
 176  * Wrappers for getting reg values.
 177  *
 178  * The $zero register does not have cpu_gpr[0] allocated -- we supply the
 179  * constant zero as a source, and an uninitialized sink as destination.
 180  *
 181  * Further, we may provide an extension for word operations.
 182  */
 183 static TCGv temp_new(DisasContext *ctx)
 184 {
 185     assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
 186     return ctx->temp[ctx->ntemp++] = tcg_temp_new();
 187 }
 188
 189 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
 190 {
 191     TCGv t;
 192
 193     if (reg_num == 0) {
 194         return ctx->zero;
 195     }
 196
 197     switch (ctx->w ? ext : EXT_NONE) {
 198     case EXT_NONE:
 199         return cpu_gpr[reg_num];
 200     case EXT_SIGN:
 201         t = temp_new(ctx);
 202         tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 203         return t;
 204     case EXT_ZERO:
 205         t = temp_new(ctx);
 206         tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 207         return t;
 208     }
 209     g_assert_not_reached();
 210 }
 211
 212 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 213 {
 214     if (reg_num == 0 || ctx->w) {
 215         return temp_new(ctx);
 216     }
 217     return cpu_gpr[reg_num];
 218 }
 219
 220 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
 221 {
 222     if (reg_num != 0) {
 223         if (ctx->w) {
 224             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
 225         } else {
 226             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
 227         }
 228     }
 229 }
 230
 231 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 232 {
 233     target_ulong next_pc;
 234
 235     /* check misaligned: */
 236     next_pc = ctx->base.pc_next + imm;
 237     if (!has_ext(ctx, RVC)) {
 238         if ((next_pc & 0x3) != 0) {
 239             gen_exception_inst_addr_mis(ctx);
 240             return;
 241         }
 242     }
 243     if (rd != 0) {
 244         tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
 245     }
 246
 247     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
 248     ctx->base.is_jmp = DISAS_NORETURN;
 249 }
 250
 251 #ifndef CONFIG_USER_ONLY
 252 /* The states of mstatus_fs are:
 253  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
 254  * We will have already diagnosed disabled state,
 255  * and need to turn initial/clean into dirty.
 256  */
 257 static void mark_fs_dirty(DisasContext *ctx)
 258 {
 259     TCGv tmp;
 260     target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 261
 262     if (ctx->mstatus_fs != MSTATUS_FS) {
 263         /* Remember the state change for the rest of the TB. */
 264         ctx->mstatus_fs = MSTATUS_FS;
 265
 266         tmp = tcg_temp_new();
 267         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 268         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 269         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 270         tcg_temp_free(tmp);
 271     }
 272
 273     if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
 274         /* Remember the stage change for the rest of the TB. */
 275         ctx->mstatus_hs_fs = MSTATUS_FS;
 276
 277         tmp = tcg_temp_new();
 278         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 279         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 280         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 281         tcg_temp_free(tmp);
 282     }
 283 }
 284 #else
 285 static inline void mark_fs_dirty(DisasContext *ctx) { }
 286 #endif
 287
 288 static void gen_set_rm(DisasContext *ctx, int rm)
 289 {
 290     if (ctx->frm == rm) {
 291         return;
 292     }
 293     ctx->frm = rm;
 294     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
 295 }
 296
 297 static int ex_plus_1(DisasContext *ctx, int nf)
 298 {
 299     return nf + 1;
 300 }
 301
 302 #define EX_SH(amount) \
 303     static int ex_shift_##amount(DisasContext *ctx, int imm) \
 304     {                                         \
 305         return imm << amount;                 \
 306     }
 307 EX_SH(1)
 308 EX_SH(2)
 309 EX_SH(3)
 310 EX_SH(4)
 311 EX_SH(12)
 312
 313 #define REQUIRE_EXT(ctx, ext) do { \
 314     if (!has_ext(ctx, ext)) {      \
 315         return false;              \
 316     }                              \
 317 } while (0)
 318
 319 #define REQUIRE_32BIT(ctx) do { \
 320     if (!is_32bit(ctx)) {       \
 321         return false;           \
 322     }                           \
 323 } while (0)
 324
 325 #define REQUIRE_64BIT(ctx) do { \
 326     if (is_32bit(ctx)) {        \
 327         return false;           \
 328     }                           \
 329 } while (0)
 330
 331 static int ex_rvc_register(DisasContext *ctx, int reg)
 332 {
 333     return 8 + reg;
 334 }
 335
 336 static int ex_rvc_shifti(DisasContext *ctx, int imm)
 337 {
 338     /* For RV128 a shamt of 0 means a shift by 64. */
 339     return imm ? imm : 64;
 340 }
 341
 342 /* Include the auto-generated decoder for 32 bit insn */
 343 #include "decode-insn32.c.inc"
 344
 345 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
 346                              void (*func)(TCGv, TCGv, target_long))
 347 {
 348     TCGv dest = dest_gpr(ctx, a->rd);
 349     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 350
 351     func(dest, src1, a->imm);
 352
 353     gen_set_gpr(ctx, a->rd, dest);
 354     return true;
 355 }
 356
 357 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
 358                              void (*func)(TCGv, TCGv, TCGv))
 359 {
 360     TCGv dest = dest_gpr(ctx, a->rd);
 361     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 362     TCGv src2 = tcg_constant_tl(a->imm);
 363
 364     func(dest, src1, src2);
 365
 366     gen_set_gpr(ctx, a->rd, dest);
 367     return true;
 368 }
 369
 370 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
 371                       void (*func)(TCGv, TCGv, TCGv))
 372 {
 373     TCGv dest = dest_gpr(ctx, a->rd);
 374     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 375     TCGv src2 = get_gpr(ctx, a->rs2, ext);
 376
 377     func(dest, src1, src2);
 378
 379     gen_set_gpr(ctx, a->rd, dest);
 380     return true;
 381 }
 382
 383 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
 384                              void (*func)(TCGv, TCGv, target_long))
 385 {
 386     TCGv dest, src1;
 387     int max_len = oper_len(ctx);
 388
 389     if (a->shamt >= max_len) {
 390         return false;
 391     }
 392
 393     dest = dest_gpr(ctx, a->rd);
 394     src1 = get_gpr(ctx, a->rs1, ext);
 395
 396     func(dest, src1, a->shamt);
 397
 398     gen_set_gpr(ctx, a->rd, dest);
 399     return true;
 400 }
 401
 402 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
 403                              void (*func)(TCGv, TCGv, TCGv))
 404 {
 405     TCGv dest, src1, src2;
 406     int max_len = oper_len(ctx);
 407
 408     if (a->shamt >= max_len) {
 409         return false;
 410     }
 411
 412     dest = dest_gpr(ctx, a->rd);
 413     src1 = get_gpr(ctx, a->rs1, ext);
 414     src2 = tcg_constant_tl(a->shamt);
 415
 416     func(dest, src1, src2);
 417
 418     gen_set_gpr(ctx, a->rd, dest);
 419     return true;
 420 }
 421
 422 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
 423                       void (*func)(TCGv, TCGv, TCGv))
 424 {
 425     TCGv dest = dest_gpr(ctx, a->rd);
 426     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 427     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 428     TCGv ext2 = tcg_temp_new();
 429
 430     tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
 431     func(dest, src1, ext2);
 432
 433     gen_set_gpr(ctx, a->rd, dest);
 434     tcg_temp_free(ext2);
 435     return true;
 436 }
 437
 438 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
 439                       void (*func)(TCGv, TCGv))
 440 {
 441     TCGv dest = dest_gpr(ctx, a->rd);
 442     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 443
 444     func(dest, src1);
 445
 446     gen_set_gpr(ctx, a->rd, dest);
 447     return true;
 448 }
 449
 450 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 451 {
 452     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 453     CPUState *cpu = ctx->cs;
 454     CPURISCVState *env = cpu->env_ptr;
 455
 456     return cpu_ldl_code(env, pc);
 457 }
 458
 459 /* Include insn module translation function */
 460 #include "insn_trans/trans_rvi.c.inc"
 461 #include "insn_trans/trans_rvm.c.inc"
 462 #include "insn_trans/trans_rva.c.inc"
 463 #include "insn_trans/trans_rvf.c.inc"
 464 #include "insn_trans/trans_rvd.c.inc"
 465 #include "insn_trans/trans_rvh.c.inc"
 466 #include "insn_trans/trans_rvv.c.inc"
 467 #include "insn_trans/trans_rvb.c.inc"
 468 #include "insn_trans/trans_privileged.c.inc"
 469
 470 /* Include the auto-generated decoder for 16 bit insn */
 471 #include "decode-insn16.c.inc"
 472
 473 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 474 {
 475     /* check for compressed insn */
 476     if (extract16(opcode, 0, 2) != 3) {
 477         if (!has_ext(ctx, RVC)) {
 478             gen_exception_illegal(ctx);
 479         } else {
 480             ctx->pc_succ_insn = ctx->base.pc_next + 2;
 481             if (!decode_insn16(ctx, opcode)) {
 482                 gen_exception_illegal(ctx);
 483             }
 484         }
 485     } else {
 486         uint32_t opcode32 = opcode;
 487         opcode32 = deposit32(opcode32, 16, 16,
 488                              translator_lduw(env, &ctx->base,
 489                                              ctx->base.pc_next + 2));
 490         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 491         if (!decode_insn32(ctx, opcode32)) {
 492             gen_exception_illegal(ctx);
 493         }
 494     }
 495 }
 496
 497 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 498 {
 499     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 500     CPURISCVState *env = cs->env_ptr;
 501     RISCVCPU *cpu = RISCV_CPU(cs);
 502     uint32_t tb_flags = ctx->base.tb->flags;
 503
 504     ctx->pc_succ_insn = ctx->base.pc_first;
 505     ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
 506     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
 507     ctx->priv_ver = env->priv_ver;
 508 #if !defined(CONFIG_USER_ONLY)
 509     if (riscv_has_ext(env, RVH)) {
 510         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
 511     } else {
 512         ctx->virt_enabled = false;
 513     }
 514 #else
 515     ctx->virt_enabled = false;
 516 #endif
 517     ctx->xl = env->misa_mxl;
 518     ctx->misa_ext = env->misa_ext;
 519     ctx->frm = -1;  /* unknown rounding mode */
 520     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 521     ctx->vlen = cpu->cfg.vlen;
 522     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
 523     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
 524     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
 525     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
 526     ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
 527     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
 528     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
 529     ctx->cs = cs;
 530     ctx->w = false;
 531     ctx->ntemp = 0;
 532     memset(ctx->temp, 0, sizeof(ctx->temp));
 533
 534     ctx->zero = tcg_constant_tl(0);
 535 }
 536
 537 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 538 {
 539 }
 540
 541 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 542 {
 543     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 544
 545     tcg_gen_insn_start(ctx->base.pc_next);
 546 }
 547
 548 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 549 {
 550     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 551     CPURISCVState *env = cpu->env_ptr;
 552     uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 553
 554     decode_opc(env, ctx, opcode16);
 555     ctx->base.pc_next = ctx->pc_succ_insn;
 556     ctx->w = false;
 557
 558     for (int i = ctx->ntemp - 1; i >= 0; --i) {
 559         tcg_temp_free(ctx->temp[i]);
 560         ctx->temp[i] = NULL;
 561     }
 562     ctx->ntemp = 0;
 563
 564     if (ctx->base.is_jmp == DISAS_NEXT) {
 565         target_ulong page_start;
 566
 567         page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
 568         if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
 569             ctx->base.is_jmp = DISAS_TOO_MANY;
 570         }
 571     }
 572 }
 573
 574 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 575 {
 576     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 577
 578     switch (ctx->base.is_jmp) {
 579     case DISAS_TOO_MANY:
 580         gen_goto_tb(ctx, 0, ctx->base.pc_next);
 581         break;
 582     case DISAS_NORETURN:
 583         break;
 584     default:
 585         g_assert_not_reached();
 586     }
 587 }
 588
 589 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
 590 {
 591 #ifndef CONFIG_USER_ONLY
 592     RISCVCPU *rvcpu = RISCV_CPU(cpu);
 593     CPURISCVState *env = &rvcpu->env;
 594 #endif
 595
 596     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
 597 #ifndef CONFIG_USER_ONLY
 598     qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
 599 #endif
 600     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
 601 }
 602
 603 static const TranslatorOps riscv_tr_ops = {
 604     .init_disas_context = riscv_tr_init_disas_context,
 605     .tb_start           = riscv_tr_tb_start,
 606     .insn_start         = riscv_tr_insn_start,
 607     .translate_insn     = riscv_tr_translate_insn,
 608     .tb_stop            = riscv_tr_tb_stop,
 609     .disas_log          = riscv_tr_disas_log,
 610 };
 611
 612 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
 613 {
 614     DisasContext ctx;
 615
 616     translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
 617 }
 618
 619 void riscv_translate_init(void)
 620 {
 621     int i;
 622
 623     /*
 624      * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
 625      * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
 626      * unless you specifically block reads/writes to reg 0.
 627      */
 628     cpu_gpr[0] = NULL;
 629
 630     for (i = 1; i < 32; i++) {
 631         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 632             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
 633     }
 634
 635     for (i = 0; i < 32; i++) {
 636         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
 637             offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
 638     }
 639
 640     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
 641     cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
 642     load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
 643                              "load_res");
 644     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
 645                              "load_val");
 646 }