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target/riscv: Rename IBEX CPU init routine
2020-06-19
Bin Meng
target/riscv: Rename
IBEX CPU init routine
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
hw/
r
iscv
:
sifive_u: Add a new property msel for MS
E
L
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
h
w/riscv: sifi
v
e_u: Rename serial prope
r
ty get/set
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
h
w/riscv:
sif
i
v
e_u: Ad
d
reset funct
i
o
nality
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/
r
iscv: sifive_gpio:
Do not blindly trigger ou
t
pu
t
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
B
i
n Meng
hw/riscv: sif
i
ve_u: Hook a G
P
IO controller
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Me
n
g
h
w/
r
iscv: si
f
ive_gpio: Add a new 'ngpio' p
r
operty
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_gp
i
o: Cl
e
an up
t
h
e
codes
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
M
eng
hw/riscv: sifive_u: Generate device tre
e
n
o
de for
O
TP
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
n
g
h
w
/riscv: s
i
five_u
:
S
i
mplify
t
he GEM IRQ connect
c
ode
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw
/
riscv: opent
i
tan
:
Re
m
ove the
r
i
sc
v
_ prefi
x
of
the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
hw/riscv: s
i
five_e: R
e
move the riscv_ pref
i
x of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin
Meng
riscv: Keep the CPU in
i
t
r
outine n
a
mes consistent
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Meng
riscv: Generalize CPU init routine for the
i
m
a
c
u C
P
U
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin Men
g
r
i
s
cv: Gener
a
lize
CPU
i
nit routine
f
or the gcsu C
P
U
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-19
Bin M
e
ng
riscv: Generalize
C
PU i
n
it
r
o
utine for
t
h
e bas
e
CPU
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
ng
hw/riscv: vi
r
t
: Remove th
e
riscv_ prefix
o
f the machine
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin Meng
hw/ri
s
cv: si
f
iv
e
_
u
: Remove the riscv_
prefix
of the
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
Bin M
e
ng
riscv
:
C
h
a
nge the default behavi
o
r if no
-
bios option
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
2020-06-03
B
i
n Meng
r
i
s
cv:
S
u
ppress the err
o
r rep
o
r
t
for QEMU testing wi
t
h
.
.
.
Signed-off-by: Bin Meng <
bin.meng@windriver.com
>
commit
|
commitdiff
|
tree
