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meson.build: Merge riscv32 and riscv64 cpu family
2021-11-17 Richard Hendersonmeson.build: Merge riscv32 and riscv64 cpu family
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-11-17 Bin Mengtarget/riscv: machine: Sort the .subsections
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2021-10-29 Chih-Min Chaotarget/riscv: change the api for RVF/RVD fmin/fmax
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-29 Chih-Min Chaosoftfloat: add APIs to handle alternative sNaN propagation...
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2021-10-29 Jose Martinstarget/riscv: remove force HS exception
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-29 Jose Martinstarget/riscv: fix VS interrupts forwarding to HS
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alexey Baturotarget/riscv: Allow experimental J-ext to be turned on
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2021-10-28 Anatoly Parshintsevtarget/riscv: Implement address masking functions required...
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2021-10-28 Alexey Baturotarget/riscv: Support pointer masking for RISC-V for...
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2021-10-28 Alexey Baturotarget/riscv: Print new PM CSRs in QEMU logs
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2021-10-28 Alexey Baturotarget/riscv: Add J extension state description
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2021-10-28 Alexey Baturotarget/riscv: Support CSRs required for RISC-V PM extension...
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2021-10-28 Alexey Baturotarget/riscv: Add CSR defines for RISC-V PM extension
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2021-10-28 Alexey Baturotarget/riscv: Add J-extension into RISC-V
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2021-10-28 Alistair Francishw/riscv: opentitan: Fixup the PLIC context addresses
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: virt: Use the PLIC config helper function
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2021-10-28 Alistair Francishw/riscv: microchip_pfsoc: Use the PLIC config helper...
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2021-10-28 Alistair Francishw/riscv: sifive_u: Use the PLIC config helper function
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2021-10-28 Alistair Francishw/riscv: boot: Add a PLIC config string function
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2021-10-28 Alistair Francishw/riscv: virt: Don't use a macro for the PLIC configuration
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2021-10-22 Bin Menghw/riscv: spike: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: sifive_u: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: sifive_e: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: shakti_c: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: opentitan: Use MachineState::ram and MachineClass...
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2021-10-22 Bin Menghw/riscv: microchip_pfsoc: Use MachineState::ram and...
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the irq_request function
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the realize function
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2021-10-22 Alistair Francishw/intc: sifive_plic: Move the properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: Remove the Ibex PLIC
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2021-10-22 Alistair Francishw/riscv: opentitan: Update to the latest build
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2021-10-22 Richard Hendersontarget/riscv: Compute mstatus.sd on demand
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Richard Hendersontarget/riscv: Use riscv_csrrw_debug for cpu_dump
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2021-10-22 Richard Hendersontarget/riscv: Use gen_shift*_per_ol for RVB, RVI
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2021-10-22 Richard Hendersontarget/riscv: Use gen_unary_per_ol for RVB
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2021-10-22 Richard Hendersontarget/riscv: Adjust trans_rev8_32 for riscv64
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2021-10-22 Richard Hendersontarget/riscv: Use gen_arith_per_ol for RVM
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2021-10-21 Richard Hendersontarget/riscv: Replace DisasContext.w with DisasContext.ol
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2021-10-21 Richard Hendersontarget/riscv: Replace is_32bit with get_xl/get_xlen
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2021-10-21 Richard Hendersontarget/riscv: Properly check SEW in amo_op
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Richard Hendersontarget/riscv: Use REQUIRE_64BIT in amo_check64
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2021-10-21 Richard Hendersontarget/riscv: Add MXL/SXL/UXL to TB_FLAGS
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2021-10-21 Richard Hendersontarget/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
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2021-10-21 Richard Hendersontarget/riscv: Split misa.mxl and misa.ext
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2021-10-21 Richard Hendersontarget/riscv: Create RISCVMXL enumeration
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2021-10-21 Richard Hendersontarget/riscv: Move cpu_get_tb_cpu_state out of line
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2021-10-21 Alistair Francistarget/riscv: Organise the CPU properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Alistair Francistarget/riscv: Remove some unused macros
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2021-10-21 Frank Changtarget/riscv: fix TB_FLAGS bits overlapping bug for...
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2021-10-21 Mingwang Lihw/riscv: virt: Use machine->ram as the system memory
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Philipp Tomsichtarget/riscv: Fix orc.b implementation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Travis Geiselbrechttarget/riscv: line up all of the registers in the info...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Frank Changtarget/riscv: Pass the same value to oprsz and maxsz...
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2021-10-06 Alistair Francishw/riscv: shakti_c: Mark as not user creatable
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2021-10-06 Bin Menghw/dma: sifive_pdma: Don't run DMA when channel is...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/dma: sifive_pdma: Fix Control.claim bit detection
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
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2021-10-06 Philippe Mathieu... hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG...
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2021-10-06 Bin Menghw/char: sifive_uart: Register device in 'input' category
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Bin Menghw/char: shakti_uart: Register device in 'input' category
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2021-10-06 Bin Menghw/char: ibex_uart: Register device in 'input' category
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2021-10-06 Frank Changtarget/riscv: Set mstatus_hs.[SD|FS] bits if Clean...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichdisas/riscv: Add Zb[abcs] instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Remove RVB (replaced by Zb[abcs])
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add zext.h instructions to Zbb, removing...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add rev8 instruction, removing grev/grevi
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add a REQUIRE_32BIT macro
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2021-10-06 Philipp Tomsichtarget/riscv: Add orc.b instruction for Zbb, removing...
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbb-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add instructions of the Zbc-extension
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zbs-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Remove shift-one instructions (proposed...
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2021-10-06 Philipp Tomsichtarget/riscv: Remove the W-form instructions from Zbs
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2021-10-06 Philipp Tomsichtarget/riscv: Reassign instructions to the Zba-extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
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2021-10-06 Philipp Tomsichtarget/riscv: clwz must ignore high bits (use shift...
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2021-10-06 Philipp Tomsichtarget/riscv: fix clzw implementation to operate on...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Philipp Tomsichtarget/riscv: Introduce temporary in gen_add_uw()
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2021-09-21 Alistair Francishw/riscv: opentitan: Correct the USB Dev address
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Bin Mengtarget/riscv: csr: Rename HCOUNTEREN_CY and friends
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Frank Changtarget/riscv: Backup/restore mstatus.SD bit when virtual...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Bin Mengdocs/system/riscv: sifive_u: Update U-Boot instructions
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2021-09-20 Frank Changhw/dma: sifive_pdma: don't set Control.error if 0 bytes...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Green Wanhw/dma: sifive_pdma: allow non-multiple transaction...
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2021-09-20 Frank Changhw/dma: sifive_pdma: claim bit must be set before DMA...
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2021-09-20 Frank Changhw/dma: sifive_pdma: reset Next* registers when Control...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Add optional ACLINT support to virt...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/riscv: virt: Re-factor FDT generation
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2021-09-20 Anup Patelhw/intc: Upgrade the SiFive CLINT implementation to...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Anup Patelhw/intc: Rename sifive_clint sources to riscv_aclint...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francissifive_u: Connect the SiFive PWM device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/timer: Add SiFive PWM support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_timer: Convert the timer to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_plic: Convert the PLIC to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_plic: Convert the PLIC to use RISC-V...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Expose interrupt pending bits as GPIO...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 LIU Zhiweitarget/riscv: Fix satp write
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Update the ePMP CSR address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU