| commit | ef6310064820183cce7c5969cae293e680c57679 | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Mon, 18 Oct 2021 02:38:39 +0000 (18 12:38 +1000) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 22 Oct 2021 13:35:47 +0000 (22 23:35 +1000) | ||
| tree | b5ffff1909b00321badc12c0f31d987d1aa70a6f | treesnapshot (tar.gz zip) |
| parent | b550f89457ef5022231f8255ae1a6ba496c492b1 | commitdiff |
hw/riscv: opentitan: Update to the latest build
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
| hw/riscv/opentitan.c | diffblobblamehistory | |
| include/hw/riscv/opentitan.h | diffblobblamehistory |