| 2022-03-03 | Anup Patel | hw/riscv: virt: Increase maximum number of allowed... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-03 | Anup Patel | docs/system: riscv: Document AIA options for virt machine Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-03 | Anup Patel | hw/riscv: virt: Add optional AIA IMSIC support to virt... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-03 | Anup Patel | hw/intc: Add RISC-V AIA IMSIC device emulation Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-03 | Anup Patel | hw/riscv: virt: Add optional AIA APLIC support to virt... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | hw/intc: Add RISC-V AIA APLIC device emulation Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Allow users to force enable AIA CSRs... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | hw/riscv: virt: Use AIA INTC compatible string when... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA IMSIC interface CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA xiselect and xireg CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA mtopi, stopi, and vstopi... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA interrupt filtering CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA hvictl and hviprioX CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA CSRs for 64 local interrupts... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement AIA local interrupt priorities Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Allow AIA device emulation to set ireg... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Add defines for AIA CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Add AIA cpu feature Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Allow setting CPU feature from machine... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Improve delivery of guest external interrupts Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement hgeie and hgeip CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Implement SGEIP bit in hip and hie CSRs Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-02-16 | Anup Patel | target/riscv: Fix trap cause for RV32 HS-mode CSR access... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-01-21 | Anup Patel | roms/opensbi: Remove ELF images Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-01-21 | Anup Patel | hw/riscv: Remove macros for ELF BIOS image names Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-01-21 | Anup Patel | hw/riscv: spike: Allow using binary firmware as bios Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2021-09-20 | Anup Patel | hw/riscv: virt: Add optional ACLINT support to virt... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-09-20 | Anup Patel | hw/riscv: virt: Re-factor FDT generation Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-09-20 | Anup Patel | hw/intc: Upgrade the SiFive CLINT implementation to... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-09-20 | Anup Patel | hw/intc: Rename sifive_clint sources to riscv_aclint... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-12-18 | Anup Patel | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-11-03 | Anup Patel | hw/riscv: virt: Allow passing custom DTB Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-11-03 | Anup Patel | hw/riscv: sifive_u: Allow passing custom DTB Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-25 | Anup Patel | hw/riscv: virt: Allow creating multiple NUMA sockets Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-25 | Anup Patel | hw/riscv: spike: Allow creating multiple NUMA sockets Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-25 | Anup Patel | hw/riscv: Add helpers for RISC-V multi-socket NUMA... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-25 | Anup Patel | hw/riscv: Allow creating multiple instances of PLIC Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-25 | Anup Patel | hw/riscv: Allow creating multiple instances of CLINT Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-04-29 | Anup Patel | hw/riscv/spike: Allow more than one CPUs Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-04-29 | Anup Patel | hw/riscv/spike: Allow loading firmware separately using... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-04-29 | Anup Patel | hw/riscv: Add optional symbol callback ptr to riscv_load_fir... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-04-29 | Anup Patel | riscv: Fix Stage2 SV32 page table walk Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-02-27 | Anup Patel | hw/riscv: Provide rdtime callback for TCG in CLINT... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-02-27 | Anup Patel | target/riscv: Emulate TIME CSRs for privileged mode Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-02-10 | Anup Patel | MAINTAINERS: Add maintainer entry for Goldfish RTC Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-02-10 | Anup Patel | riscv: virt: Use Goldfish RTC device Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-02-10 | Anup Patel | hw: rtc: Add Goldfish RTC device Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-02-10 | Anup Patel | riscv/virt: Add syscon reboot and poweroff DT nodes Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2018-12-20 | Anup Patel | target/riscv/pmp.c: Fix pmp_decode_napot() Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2018-12-20 | Anup Patel | sifive_u: Set 'clock-frequency' DT property for SiFive... Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2018-12-20 | Anup Patel | sifive_u: Add clock DT node for GEM ethernet Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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