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hw/riscv/boot.c: use MachineState in riscv_load_kernel()
2023-01-20 Daniel Henrique... hw/riscv/boot.c: use MachineState in riscv_load_kernel()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-01-20 Daniel Henrique... hw/riscv/boot.c: use MachineState in riscv_load_initrd()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-01-20 Daniel Henrique... hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
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2023-01-20 Daniel Henrique... hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
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2023-01-20 Daniel Henrique... hw/riscv/spike.c: load initrd right after riscv_load_kernel()
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2023-01-20 Daniel Henrique... hw/riscv/boot.c: exit early if filename is NULL in...
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2023-01-20 Daniel Henrique... hw/riscv/sifive_u: use 'fdt' from MachineState
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2023-01-20 Daniel Henrique... hw/riscv/spike: use 'fdt' from MachineState
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2023-01-20 Daniel Henrique... tests/avocado: add RISC-V OpenSBI boot test
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2023-01-20 Dongxue Zhangtarget/riscv/cpu.c: Fix elen check
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2023-01-20 Bin Menghw/riscv: spike: Decouple create_fdt() dependency to...
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2023-01-20 Bin Menghw/riscv/boot.c: Introduce riscv_find_firmware()
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2023-01-20 Daniel Henrique... hw/riscv/boot.c: introduce riscv_default_firmware_name()
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2023-01-20 Daniel Henrique... hw/riscv/boot.c: make riscv_find_firmware() static
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2023-01-20 Bin Menghw/riscv: spike: Remove the out-of-date comments
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2023-01-20 Bin Menghw/char: riscv_htif: Support console output via proxy...
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2023-01-20 Bin Menghw/char: riscv_htif: Remove forward declarations for...
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2023-01-20 Bin Menghw/char: riscv_htif: Move registers from CPUArchState...
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2023-01-20 Bin Menghw/char: riscv_htif: Use conventional 's' for HTIFState
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2023-01-20 Bin Menghw/char: riscv_htif: Drop useless assignment of memory...
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2023-01-20 Bin Menghw/char: riscv_htif: Drop {to, from}host_size in HTIFState
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2023-01-20 Bin Menghw/char: riscv_htif: Avoid using magic numbers
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2023-01-06 Bin Menghw/intc: sifive_plic: Fix the pending register range...
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2023-01-06 Bin Menghw/riscv: opentitan: Drop "hartid-base" and "priority...
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2023-01-06 Bin Menghw/intc: sifive_plic: Change "priority-base" to start...
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2023-01-06 Bin Menghw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
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2023-01-06 Bin Menghw/riscv: sifive_u: Avoid using magic number for "riscv...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-01-06 Bin Menghw/riscv: sifive_e: Fix the number of interrupt sources...
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2023-01-06 Bin Menghw/riscv: microchip_pfsoc: Fix the number of interrupt...
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2023-01-06 Bin Menghw/intc: sifive_plic: Update "num-sources" property...
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2023-01-06 Bin Menghw/intc: sifive_plic: Use error_setg() to propagate...
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2023-01-06 Bin Menghw/intc: sifive_plic: Improve robustness of the PLIC...
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2023-01-06 Bin Menghw/intc: sifive_plic: Drop PLICMode_H
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2023-01-06 Bin Menghw/riscv: spike: Remove misleading comments
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2023-01-06 Bin Menghw/riscv: Sort machines Kconfig options in alphabetical...
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2023-01-06 Bin Menghw/riscv: Fix opentitan dependency to SIFIVE_PLIC
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2023-01-06 Bin Menghw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt...
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2023-01-06 Bin Menghw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
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2023-01-06 Christoph MuellnerRISC-V: Add Zawrs ISA extension support
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2023-01-06 Bin Mengtarget/riscv: Clear mstatus.MPRV when leaving M-mode...
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2023-01-06 Bin Mengtarget/riscv: Simplify helper_sret() a little bit
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2023-01-06 Richard Hendersontarget/riscv: Set pc_succ_insn for !rvc illegal insn
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2023-01-06 Bin Mengtarget/riscv: Fix mret exception cause when no pmp...
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2023-01-06 Jim Shuhw/intc: sifive_plic: fix out-of-bound access of source_prio...
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2023-01-06 Conor Dooleyhw/{misc, riscv}: pfsoc: add system controller as unimplemented
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2023-01-06 Conor Dooleyhw/riscv: pfsoc: add missing FICs as unimplemented
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2023-01-06 Conor Dooleyhw/misc: pfsoc: add fabric clocks to ioscb
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2023-01-06 Bin Mengtarget/riscv: Add some comments for sstatus CSR in...
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2023-01-06 Jim Shutarget/riscv: support cache-related PMU events in virtual...
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2023-01-06 Atish Patrahw/riscv: virt: Remove the redundant ipi-id property
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2023-01-06 Anup Pateltarget/riscv: Typo fix in sstc() predicate
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2023-01-06 Frédéric Pétrothw/intc: sifive_plic: Renumber the S irqs for numa...
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger_enabled field to CPURISCVState
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2023-01-06 LIU Zhiweitarget/riscv: Enable native debug itrigger
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is enabled
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is not...
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2023-01-06 Mayuresh Chitaletarget/riscv: generate virtual instruction exception
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2023-01-06 Mayuresh Chitaletarget/riscv: smstateen check for h/s/envcfg
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2023-01-06 Mayuresh Chitaletarget/riscv: Add smstateen support
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2023-01-06 Wilfred Mallawahw/riscv/opentitan: add aon_timer base unimpl
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2023-01-06 Wilfred Mallawahw/riscv/opentitan: bump opentitan
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2023-01-06 Richard Hendersontcg/riscv: Fix base register for user-only qemu_ld/st
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2023-01-06 Richard Hendersontcg/riscv: Fix reg overlap case in tcg_out_addsub2
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2023-01-06 Richard Hendersontcg/riscv: Fix range matched by TCG_CT_CONST_M12
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2023-01-06 LIU Zhiweitarget/riscv: Fix PMP propagation for tlb
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2022-10-14 Alistair Francistarget/riscv: pmp: Fixup TLB size calculation
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2022-10-14 Jim Shuhw/intc: sifive_plic: change interrupt priority register...
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2022-10-14 Jim Shuhw/intc: sifive_plic: fix hard-coded max priority level
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2022-10-14 Yang Liudisas/riscv.c: rvv: Add disas support for vector instructions
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2022-10-14 Sunil V Lhw/riscv: virt: Enable booting S-mode firmware from...
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2022-10-14 Sunil V Lhw/riscv: virt: Move create_fw_cfg() prior to loading...
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2022-10-14 Sunil V Lhw/arm, loongarch: Move load_image_to_fw_cfg() to common...
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2022-10-14 Wilfred Mallawahw/ssi: ibex_spi: fixup/add rw1c functionality
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2022-10-14 Wilfred Mallawahw/ssi: ibex_spi: fixup coverity issue
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2022-10-14 Bin Menghw/riscv: Update comment for qtest check in riscv_find_firmw...
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2022-09-27 Yang Liutarget/riscv: rvv-1.0: vf[w]redsum distinguish between...
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2022-09-27 Yang Liutarget/riscv: rvv-1.0: Simplify vfwredsum code
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2022-09-27 Frank Changtarget/riscv: debug: Add initial support of type 6...
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2022-09-27 Frank Changtarget/riscv: debug: Check VU/VS modes for type 2 trigger
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2022-09-27 Frank Changtarget/riscv: debug: Create common trigger actions...
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2022-09-27 Frank Changtarget/riscv: debug: Introduce tinfo CSR
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2022-09-27 Frank Changtarget/riscv: debug: Restrict the range of tselect...
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2022-09-27 Frank Changtarget/riscv: debug: Introduce tdata1, tdata2, and...
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2022-09-27 Frank Changtarget/riscv: debug: Introduce build_tdata1() to build...
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2022-09-27 Frank Changtarget/riscv: debug: Determine the trigger type from...
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2022-09-07 Atish Patratarget/riscv: Update the privilege field for sscofpmf...
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2022-09-07 Atish Patrahw/riscv: virt: Add PMU DT node to the device tree
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2022-09-07 Atish Patratarget/riscv: Add few cache related PMU events
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2022-09-07 Atish Patratarget/riscv: Simplify counter predicate function
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2022-09-07 Atish Patratarget/riscv: Add sscofpmf extension support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Add vstimecmp support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Add stimecmp support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patrahw/intc: Move mtimer/mtimecmp to aclint
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Anup Pateltarget/riscv: Use official extension names for AIA...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Rahul Pathaktarget/riscv: Add xicondops in ISA entry
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Conor Dooleyhw/core: fix platform bus node name
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Conor Dooleyhw/riscv: virt: fix syscon subnode paths
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Conor Dooleyhw/riscv: virt: fix the plic's address cells
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Conor Dooleyhw/riscv: virt: fix uart node name
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Atish Patratarget/riscv: Remove additional priv version check...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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