| commit | bc92f261519d5c77c70cf2ebcf0a3b9a414d82d0 | |
| author | Bin Meng <bmeng@tinylab.org> | |
| Sun, 11 Dec 2022 03:08:29 +0000 (11 11:08 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 6 Jan 2023 00:42:55 +0000 (6 10:42 +1000) | ||
| tree | 09e863bfecd790203d782813258b0afee4ff1688 | treesnapshot (tar.gz zip) |
| parent | a984e2b32f6da127f3b9ee1a72bde9b68effaa80 | commitdiff |
hw/intc: sifive_plic: Fix the pending register range check
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-16-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-16-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/intc/sifive_plic.c | diffblobblamehistory |