| commit | 9b246685b3dbbf21800e3a9a09f8bed384a1fb37 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Thu, 20 Oct 2022 23:38:36 +0000 (21 09:38 +1000) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 6 Jan 2023 00:42:55 +0000 (6 10:42 +1000) | ||
| tree | 7884f6e5485c6875d57741ae0818b61aa1b7fd3b | treesnapshot (tar.gz zip) |
| parent | 627227636127c44df0e01ab8fd9fae3f731fa8b0 | commitdiff |
tcg/riscv: Fix reg overlap case in tcg_out_addsub2
There was a typo using opc_addi instead of opc_add with the
two registers. While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
There was a typo using opc_addi instead of opc_add with the
two registers. While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| tcg/riscv/tcg-target.c.inc | diffblobblamehistory |