| commit | 31b9798d824512b7daf868cc8581f9a97a9d13a8 | |
| author | Frank Chang <frank.chang@sifive.com> | |
| Fri, 9 Sep 2022 13:42:12 +0000 (9 21:42 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 27 Sep 2022 01:23:57 +0000 (27 11:23 +1000) | ||
| tree | 804cae03acad52a5795b94ebbfb347c54d6be298 | treesnapshot (tar.gz zip) |
| parent | 6ea8d3fc40a8db8d22d00255cea9f9f8c927d643 | commitdiff |
target/riscv: debug: Introduce tinfo CSR
tinfo.info:
One bit for each possible type enumerated in tdata1.
If the bit is set, then that type is supported by the currently
selected trigger.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
tinfo.info:
One bit for each possible type enumerated in tdata1.
If the bit is set, then that type is supported by the currently
selected trigger.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu_bits.h | diffblobblamehistory | |
| target/riscv/csr.c | diffblobblamehistory | |
| target/riscv/debug.c | diffblobblamehistory | |
| target/riscv/debug.h | diffblobblamehistory |