target/riscv: Add few cache related PMU events
commit892320facd73136b48bb58af3bd742686eb05416
authorAtish Patra <atish.patra@wdc.com>
Wed, 24 Aug 2022 22:16:59 +0000 (24 15:16 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 7 Sep 2022 07:19:15 +0000 (7 09:19 +0200)
tree341768428045b8636be354fe309caffcefc9ec63
parentade445ef85aa0cf711a311132cb458f11f6a6d12
target/riscv: Add few cache related PMU events

Qemu can monitor the following cache related PMU events through
tlb_fill functions.

1. DTLB load/store miss
3. ITLB prefetch miss

Increment the PMU counter in tlb_fill function.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_helper.c