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2023-12-29	Juzhe-Zhong	RISC-V: Disallow transformation into VLMAX AVL for...	commit \| commitdiff \| tree
2023-12-28	Juzhe-Zhong	RISC-V: Make dynamic LMUL cost model more accurate...	commit \| commitdiff \| tree
2023-12-27	Juzhe-Zhong	RISC-V: Make known NITERS loop be aware of dynamic...	commit \| commitdiff \| tree
2023-12-26	Juzhe-Zhong	RISC-V: Fix typo	commit \| commitdiff \| tree
2023-12-26	Juzhe-Zhong	RISC-V: Some minior tweak on dynamic LMUL cost model	commit \| commitdiff \| tree
2023-12-25	Juzhe-Zhong	RISC-V: Move RVV V_REGS liveness computation into analyze_lo...	commit \| commitdiff \| tree
2023-12-25	Juzhe-Zhong	RISC-V: Add one more ASM check in PR113112-1.c	commit \| commitdiff \| tree
2023-12-24	Pan Li	RISC-V: XFail the signbit-5 run test for RVV Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-23	Juzhe-Zhong	RISC-V: Make PHI initial value occupy live V_REG in...	commit \| commitdiff \| tree
2023-12-21	Juzhe-Zhong	RISC-V: Add dynamic LMUL test for x264	commit \| commitdiff \| tree
2023-12-20	Juzhe-Zhong	RISC-V: Optimize SELECT_VL codegen when length is known...	commit \| commitdiff \| tree
2023-12-20	Juzhe-Zhong	RISC-V: Fix bug of VSETVL fusion	commit \| commitdiff \| tree
2023-12-20	demin.han	RISC-V: Fix calculation of max live vregs	commit \| commitdiff \| tree
2023-12-20	Pan Li	RISC-V: Bugfix for the const vector in single steps Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-20	Juzhe-Zhong	RISC-V: Fix ICE of moving SUBREG of vector mode to...	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Refine some codes of expand_const_vector [NFC]	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Force scalable vector on all vsetvl tests	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Fix FAIL of dynamic-lmul2-7.c	commit \| commitdiff \| tree
2023-12-19	Juzhe-Zhong	RISC-V: Remove 256/512/1024 VLS vectors	commit \| commitdiff \| tree
2023-12-18	Pan Li	RISC-V: Rename the rvv test case. Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-18	Juzhe-Zhong	RISC-V: Support one more overlap for wv instructions	commit \| commitdiff \| tree
2023-12-18	Juzhe-Zhong	RISC-V: Enable vect test for RV32	commit \| commitdiff \| tree
2023-12-18	Juzhe-Zhong	RISC-V: Fix natural regsize for fixed-vlmax of -march...	commit \| commitdiff \| tree
2023-12-18	Pan Li	RISC-V: Bugfix for the RVV const vector Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-18	Pan Li	RISC-V: Fix POLY INT handle bug Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Fix vmerge optimization bug in vec_perm vectorization	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Remove xfail for some of the SLP tests	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Adjust test	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	RISC-V: Tweak generic vector COST model	commit \| commitdiff \| tree
2023-12-15	Juzhe-Zhong	Middle-end: Do not model address cost for SELECT_VL...	commit \| commitdiff \| tree
2023-12-14	Juzhe-Zhong	RISC-V: Add failed SLP testcase	commit \| commitdiff \| tree
2023-12-14	Juzhe-Zhong	RISC-V: Add RVV builtin vectorization cost model	commit \| commitdiff \| tree
2023-12-13	Pan Li	RISC-V: Refine test cases for both PR112929 and PR112988 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-13	Juzhe-Zhong	RISC-V: Postpone full available optimization [VSETVL...	commit \| commitdiff \| tree
2023-12-13	demin.han	RISC-V: Fix dynamic lmul tests depended on abi	commit \| commitdiff \| tree
2023-12-13	Juzhe-Zhong	Middle-end: Adjust decrement IV style partial vectorization...	commit \| commitdiff \| tree
2023-12-12	Juzhe-Zhong	RISC-V: Apply vla vs. vls mode heuristic vector COST...	commit \| commitdiff \| tree
2023-12-12	Juzhe-Zhong	RISC-V: Refactor Dynamic LMUL codes	commit \| commitdiff \| tree
2023-12-12	Pan Li	RISC-V: Disable RVV VCOMPRESS avl propagation Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-12	Juzhe-Zhong	RISC-V: Move RVV POLY VALUE estimation from riscv.cc...	commit \| commitdiff \| tree
2023-12-11	Juzhe-Zhong	RISC-V: Support highest overlap for wv instructions	commit \| commitdiff \| tree
2023-12-09	Juzhe-Zhong	RISC-V: Fix VLS mode movmiaslign bug	commit \| commitdiff \| tree
2023-12-08	Pan Li	RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-07	Juzhe-Zhong	RISC-V: Support interleave vector with different step...	commit \| commitdiff \| tree
2023-12-06	Juzhe-Zhong	RISC-V: Fix VSETVL PASS bug	commit \| commitdiff \| tree
2023-12-05	Juzhe-Zhong	RISC-V: Block VLSmodes according to TARGET_MAX_LMUL...	commit \| commitdiff \| tree
2023-12-05	Juzhe-Zhong	RISC-V: Add blocker for gather/scatter auto-vectorization	commit \| commitdiff \| tree
2023-12-04	Juzhe-Zhong	RISC-V: Fix overlap group incorrect overlap on v0	commit \| commitdiff \| tree
2023-12-04	Juzhe-Zhong	RISC-V: Support highest-number regno overlap for widen...	commit \| commitdiff \| tree
2023-12-04	Pan Li	RISC-V: Add test case for bug PR112813 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-04	Juzhe-Zhong	RISC-V: Robostify the W43, W86, W87 constraint enabled...	commit \| commitdiff \| tree
2023-12-03	Pan Li	RISC-V: Fix typo in test abi configuration Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-12-02	Juzhe-Zhong	RISC-V: Fix incorrect combine of extended scalar pattern	commit \| commitdiff \| tree
2023-12-02	Pan Li	RISC-V: Bugfix for legitimize move when get vec mode... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-30	Juzhe-Zhong	RISC-V: Support widening register overlap for vf4/vf8	commit \| commitdiff \| tree
2023-11-30	Juzhe-Zhong	RISC-V: Rename vconstraint into group_overlap	commit \| commitdiff \| tree
2023-11-30	Juzhe-Zhong	RISC-V: Support highpart overlap for vext.vf	commit \| commitdiff \| tree
2023-11-29	Juzhe-Zhong	RISC-V: Support highpart register overlap for vwcvt	commit \| commitdiff \| tree
2023-11-29	Pan Li	RISC-V: Bugfix for ICE in block move when zve32f Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-28	Juzhe-Zhong	RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization	commit \| commitdiff \| tree
2023-11-28	Juzhe-Zhong	RISC-V: Fix VSETVL PASS regression	commit \| commitdiff \| tree
2023-11-27	Juzhe-Zhong	RISC-V: Remove incorrect function gate gather_scatter_valid_...	commit \| commitdiff \| tree
2023-11-26	Juzhe-Zhong	RISC-V: Disable AVL propagation of slidedown instructions	commit \| commitdiff \| tree
2023-11-26	Juzhe-Zhong	RISC-V: Fix typo	commit \| commitdiff \| tree
2023-11-24	Juzhe-Zhong	RISC-V: Fix inconsistency among all vectorization hooks	commit \| commitdiff \| tree
2023-11-24	Juzhe-Zhong	RISC-V: Optimize a special case of VLA SLP	commit \| commitdiff \| tree
2023-11-24	Juzhe-Zhong	RISC-V: Disable BSWAP optimization for NUNITS < 4	commit \| commitdiff \| tree
2023-11-23	Juzhe-Zhong	RISC-V: Add wrapper for emit vec_extract[NFC]	commit \| commitdiff \| tree
2023-11-23	Juzhe-Zhong	RISC-V: Refine some codes of riscv-v.cc[NFC]	commit \| commitdiff \| tree
2023-11-23	Pan Li	DSE: Allow vector type for get_stored_val when read... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-22	Juzhe-Zhong	RISC-V: Fix incorrect use of vcompress in permutation...	commit \| commitdiff \| tree
2023-11-21	Juzhe-Zhong	RISC-V: Disallow COSNT_VECTOR for DI on RV32	commit \| commitdiff \| tree
2023-11-20	Juzhe-Zhong	RISC-V: Fix intermediate mode on slide1 instruction...	commit \| commitdiff \| tree
2023-11-19	Juzhe-Zhong	RISC-V: Optimize constant AVL for LRA pattern	commit \| commitdiff \| tree
2023-11-19	Juzhe-Zhong	RISC-V: Fix bug of tuple move splitter	commit \| commitdiff \| tree
2023-11-18	Juzhe-Zhong	RISC-V: Refactor RVV iterators[NFC]	commit \| commitdiff \| tree
2023-11-15	Juzhe-Zhong	RISC-V: Support trailing vec_init optimization	commit \| commitdiff \| tree
2023-11-15	Pan Li	RISC-V: Refine the mask generation for vec_init case 2 Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-15	Juzhe-Zhong	RISC-V: Disallow RVV mode address for any load/store...	commit \| commitdiff \| tree
2023-11-14	Juzhe-Zhong	RISC-V: Fix init-2.c assembly check	commit \| commitdiff \| tree
2023-11-13	Juzhe-Zhong	RISC-V: Optimize combine sequence by merge approach	commit \| commitdiff \| tree
2023-11-13	Pan Li	RISC-V: Fix RVV dynamic frm tests failure Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-13	Pan Li	RISC-V: Support FP l/ll round and rint HF mode autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-11	Juzhe-Zhong	RISC-V: Add test for PR112469	commit \| commitdiff \| tree
2023-11-10	Juzhe-Zhong	Middle-end: Fix bug of induction variable vectorization...	commit \| commitdiff \| tree
2023-11-10	Juzhe-Zhong	RISC-V: Add combine optimization by slideup for vec_init...	commit \| commitdiff \| tree
2023-11-10	Juzhe-Zhong	RISC-V: Robustify vec_init pattern[NFC]	commit \| commitdiff \| tree
2023-11-10	Pan Li	Revert "RISC-V: Support vec_init for trailing same...	commit \| commitdiff \| tree
2023-11-10	Pan Li	RISC-V: Support vec_init for trailing same element Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-10	Juzhe-Zhong	test: Fix FAIL of pr97428.c for RVV	commit \| commitdiff \| tree
2023-11-10	Juzhe-Zhong	RISC-V: Move cond_copysign from combine pattern to...	commit \| commitdiff \| tree
2023-11-10	Pan Li	Internal-fn: Add FLOATN support for l/ll round and... Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-09	Pan Li	RISC-V: Refine frm emit after bb end in succ edges Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
2023-11-09	Juzhe-Zhong	RISC-V: Add PR112450 test to avoid regression	commit \| commitdiff \| tree
2023-11-09	Juzhe-Zhong	RISC-V: Fix dynamic LMUL cost model ICE	commit \| commitdiff \| tree
2023-11-09	Juzhe-Zhong	RISC-V: Fix dynamic tests [NFC]	commit \| commitdiff \| tree
2023-11-08	Juzhe-Zhong	RISC-V: Fix VSETVL VL check condition bug	commit \| commitdiff \| tree
2023-11-08	Juzhe-Zhong	test: Fix bb-slp-33.c for RVV	commit \| commitdiff \| tree
2023-11-07	Pan Li	RISC-V: Support FP floor to i/l/ll diff size autovec Signed-off-by: Pan Li <pan2.li@intel.com>	commit \| commitdiff \| tree
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