RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in...
commitd1eacedc6d9ba9f5522f2c8d49ccfdf7939ad72d
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Wed, 27 Dec 2023 02:38:26 +0000 (27 10:38 +0800)
committerPan Li <pan2.li@intel.com>
Fri, 29 Dec 2023 00:38:03 +0000 (29 08:38 +0800)
tree02bff2f39a932cf20db291a00c5dbb7c20ebd576
parent7de05ad450044927eb1eb0259d5dd1aa385f4325
RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31]

Notice we have this following situation:

        vsetivli        zero,4,e32,m1,ta,ma
        vlseg4e32.v     v4,(a5)
        vlseg4e32.v     v12,(a3)
        vsetvli a5,zero,e32,m1,tu,ma             ---> This is redundant since VLMAX AVL = 4 when it is fixed-vlmax
        vfadd.vf        v3,v13,fa0
        vfadd.vf        v1,v12,fa1
        vfmul.vv        v17,v3,v5
        vfmul.vv        v16,v1,v5

The rootcause is that we transform COND_LEN_xxx into VLMAX AVL when len == NUNITS blindly.
However, we don't need to transform all of them since when len is range of [0,31], we don't need to
consume scalar registers.

After this patch:

vsetivli zero,4,e32,m1,tu,ma
addi a4,a5,400
vlseg4e32.v v12,(a3)
vfadd.vf v3,v13,fa0
vfadd.vf v1,v12,fa1
vlseg4e32.v v4,(a4)
vfadd.vf v2,v14,fa1
vfmul.vv v17,v3,v5
vfmul.vv v16,v1,v5

Tested on both RV32 and RV64 no regression.

Ok for trunk ?

gcc/ChangeLog:

* config/riscv/riscv-v.cc (is_vlmax_len_p): New function.
(expand_load_store): Disallow transformation into VLMAX when len is in range of [0,31]
(expand_cond_len_op): Ditto.
(expand_gather_scatter): Ditto.
(expand_lanes_load_store): Ditto.
(expand_fold_extract_last): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/post-ra-avl.c: Adapt test.
* gcc.target/riscv/rvv/base/vf_avl-2.c: New test.
gcc/config/riscv/riscv-v.cc
gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c [new file with mode: 0644]