RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in...
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / base / vf_avl-2.c
blob5a94a51f30844dbcbcdd9598bb1cae4d6bb69c5a
1 /* { dg-do compile } */
2 /* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
4 float f[12][100];
6 void bad1(float v1, float v2)
8 for (int r = 0; r < 100; r += 4)
10 int i = r + 1;
11 f[0][r] = f[1][r] * (f[2][r] + v2) - f[1][i] * (f[2][i] + v1);
12 f[0][i] = f[1][r] * (f[2][i] + v1) + f[1][i] * (f[2][r] + v2);
13 f[0][r+2] = f[1][r+2] * (f[2][r+2] + v2) - f[1][i+2] * (f[2][i+2] + v1);
14 f[0][i+2] = f[1][r+2] * (f[2][i+2] + v1) + f[1][i+2] * (f[2][r+2] + v2);
18 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */
19 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */
20 /* { dg-final { scan-assembler-times {vsetivli} 2 } } */
21 /* { dg-final { scan-assembler-not {vsetvli} } } */