| commit | 71bc7c6fa116dec13ca0c636c2755d26f3341b33 | |
| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | |
| Tue, 19 Dec 2023 11:40:48 +0000 (19 19:40 +0800) | ||
| committer | Pan Li <pan2.li@intel.com> | |
| Tue, 19 Dec 2023 13:14:22 +0000 (19 21:14 +0800) | ||
| tree | 291d7ea29b367963d28e2b17a91d41b7036116f7 | treesnapshot (tar.gz zip) |
| parent | afd49e663258061a10f0f2c4a8f8aa2bf97bee42 | commitdiff |
RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV
Due to recent VLSmode changes (Change for fixing ICE and run-time FAIL).
The dump check is same as ARM SVE now. So adapt test for RISC-V.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-cond-1.c: Adapt for RISC-V.
Due to recent VLSmode changes (Change for fixing ICE and run-time FAIL).
The dump check is same as ARM SVE now. So adapt test for RISC-V.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-cond-1.c: Adapt for RISC-V.
| gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c | diffblobblamehistory |