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target/riscv: rvv: Add mask agnostic for vector mask instructions
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector mask...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector floating...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector fix...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vx instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector load...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vv instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Bin Mengdocs: List kvm as a supported accelerator on RISC-V
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Alexey Baturotarget/riscv: Fix typo and restore Pointer Masking...
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2022-09-07 Bin Mengroms/opensbi: Upgrade from v1.0 to v1.1
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Weiwei Litarget/riscv: Simplify the check in hmode to reuse...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Weiwei Litarget/riscv: Fix checks in hmode/hmode32
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2022-09-07 Weiwei Litarget/riscv: Add check for csrs existed with U extension
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2022-09-07 Weiwei Litarget/riscv: Fix checkpatch warning may triggered...
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2022-09-07 Weiwei Litarget/riscv: H extension depends on I extension
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2022-09-07 Weiwei Litarget/riscv: Add check for supported privilege mode...
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2022-09-07 Jason A. Donenfeldhw/riscv: virt: pass random seed to fdt
Cc: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Weiwei Litarget/riscv: move zmmul out of the experimental properties
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-09-07 Frédéric Pétrottarget/riscv: fix shifts shamt value for rv128c
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2022-09-07 Anup Pateltarget/riscv: Force disable extensions if priv spec...
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2022-09-07 Anup Pateltarget/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
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2022-08-01 Richard Hendersonlinux-user/riscv: Align signal frame to 16 bytes
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2022-07-27 Atish Patrahw/intc: sifive_plic: Fix multi-socket plic configuraiton
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-27 Palmer DabbeltRISC-V: Allow both Zmmul and M
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Anup Pateltarget/riscv: Update default priority table for local...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Anup Pateltarget/riscv: Remove CSRs that set/clear an IMSIC interrupt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Anup Pateltarget/riscv: Set minumum priv spec version for mcountinhibit
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2022-07-03 Alistair Francishw/riscv: boot: Reduce FDT address alignment constraints
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Anup Pateltarget/riscv: Don't force update priv spec version...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Alistair Francistarget/riscv: Ibex: Support priv version 1.11
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2022-07-03 Alistair Francistarget/riscv: Fixup MSECCFG minimum priv check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: Support mcycle/minstret write operation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: Add support for hpmcounters/hpmevents
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: Implement mcountinhibit CSR
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: pmu: Make number of counters configurable
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: pmu: Rename the counters extension to pmu
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: Implement PMU CSR predicate function...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Atish Patratarget/riscv: Fix PMU CSR predicate function
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-07-03 Nicolas Pitretarget/riscv/pmp: guard against PMP ranges with a negative...
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2022-07-03 Richard Hendersontarget/riscv: Minimize the calls to decode_save_opc
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2022-07-03 Richard Hendersontarget/riscv: Remove generate_exception_mtval
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2022-07-03 Richard Hendersontarget/riscv: Set env->bins in gen_exception_illegal
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2022-07-03 Víctor Colombotarget/riscv: Remove condition guarding register zero...
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2022-06-09 Alistair Francistarget/riscv: trans_rvv: Avoid assert for RV32 and e64
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Alistair Francistarget/riscv: Don't expose the CPU properties on names...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Add option 'rvv_ta_all_1s' to enable...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector permutation...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector mask...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector reduction...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector floating...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector fix...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vx, vvm, vxm...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector load...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vv instructions
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2022-06-09 eopXDtarget/riscv: rvv: Early exit when vstart >= vl
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2022-06-09 eopXDtarget/riscv: rvv: Rename ambiguous esz
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Prune redundant access_type parameter...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Prune redundant ESZ, DSZ parameter...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Frédéric Pétrottarget/riscv/debug.c: keep experimental rv128 support...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Andrew Brestickertarget/riscv: Wake on VS-level external interrupts
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Jamie Ileshw/core/loader: return image sizes as ssize_t
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Alistair Francishw/intc: sifive_plic: Avoid overflowing the addr_config...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Atish Patrahw/riscv: virt: Generate fw_cfg DT node correctly
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Weiwei Litarget/riscv: add support for zmmul extension v0.1
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 Alistair FrancisMAINTAINERS: Cover hw/core/uboot_image.h within Generic...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-24 Bin Menghw/core: loader: Set is_linux to true for VxWorks uImage
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-24 Bin Menghw/core: Sync uboot_image.h from U-Boot v2022.01
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2022-05-24 Hongren (Zenithal... target/riscv: add zicsr/zifencei to isa_string
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2022-05-24 Anup Patelhw/riscv: virt: Fix interrupt parent for dynamic platform...
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2022-05-24 Anup Pateltarget/riscv: Set [m|s]tval for both illegal and virtual...
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2022-05-24 Anup Pateltarget/riscv: Fix hstatus.GVA bit setting for traps...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-24 Anup Pateltarget/riscv: Fix csr number based privilege checking
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2022-05-24 Frank Changtarget/riscv: Fix typo of mimpid cpu option
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-24 Weiwei Litarget/riscv: check 'I' and 'E' after checking 'G'...
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2022-05-24 Bernhard Beschowhw/riscv/sifive_u: Resolve redundant property accessors
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2022-05-24 Bernhard Beschowhw/vfio/pci-quirks: Resolve redundant property getters
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2022-05-24 Tsukasa OItarget/riscv: Move/refactor ISA extension checks
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2022-05-24 Tsukasa OItarget/riscv: FP extension requirements
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2022-05-24 Tsukasa OItarget/riscv: Change "G" expansion
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2022-05-24 Tsukasa OItarget/riscv: Disable "G" by default
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2022-05-24 Tsukasa OItarget/riscv: Fix coding style on "G" expansion
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2022-05-24 Tsukasa OIhw/riscv: Make CPU config error handling generous ...
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2022-05-24 Tsukasa OIhw/riscv: Make CPU config error handling generous ...
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2022-05-24 Tsukasa OItarget/riscv: Add short-isa-string option
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-23 Tsukasa OItarget/riscv: Move Zhinx* extensions on ISA string
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-23 Atish Patrahw/intc: Pass correct hartid while updating mtimecmp
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-23 eopXDtarget/riscv: rvv: Fix early exit condition for whole...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-23 Dylan Reidtarget/riscv: Fix VS mode hypervisor CSR access
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: Enable TPM backends
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Add device plug support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Add support for generating platform...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Create a platform bus
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/core: Move the ARM sysbus-fdt to core
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Add a machine done notifier
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Litarget/riscv: add scalar crypto related extenstion...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Ralf Ramsauertarget/riscv: Fix incorrect PTE merge in walk_pte
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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