| commit | 62a09b9b4118ca42e79d9bd179daf7230462705b | |
| author | Weiwei Li <liweiwei@iscas.ac.cn> | |
| Mon, 18 Jul 2022 13:09:54 +0000 (18 21:09 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 7 Sep 2022 07:18:32 +0000 (7 09:18 +0200) | ||
| tree | 837d7e8adaf6ae182aaed53385a0445e9ee9d132 | treesnapshot (tar.gz zip) |
| parent | c126f83cd64883f7cb4be90a7fbf29e2be3bb9c7 | commitdiff |
target/riscv: Fix checks in hmode/hmode32
Add check for the implicit dependence between H and S
Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Add check for the implicit dependence between H and S
Csrs only existed in RV32 will not trigger virtual instruction fault
when not in RV32 based on section 8.6.1 of riscv-privileged spec
(draft-20220717)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/csr.c | diffblobblamehistory |