| 2020-02-27 | Alistair Francis | target/riscv: Extend the MIE CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set VS bits in mideleg for Hyp extension Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add virtual register swapping function Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor machine CSRs accesses Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor virtual CSRs accesses Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor CSR access functions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Dump Hypervisor registers if enabled Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Print priv and virt in disas log Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Fix CSR perm checking for HS mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the force HS exception mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the virtulisation mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Rename the H irqs to VS irqs Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the new execption numbers Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor CSRs to CPUState Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor extension Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Convert MIP CSR to target_ulong Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | MAINTAINERS: Add maintainer entry for Goldfish RTC Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | riscv: virt: Use Goldfish RTC device Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | hw: rtc: Add Goldfish RTC device Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Keith Packard | riscv: Separate FPU register size from core register... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | riscv/virt: Add syscon reboot and poweroff DT nodes Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: update mstatus.SD when FS is set dirty Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: fsd/fsw doesn't dirty FP state Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: Fix tb->flags FS status Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | Yiting Wang | riscv: Set xPIE to 1 after xRET Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | Pan Nengyuan | riscv/sifive_u: fix a memory leak in soc_realize() Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-25 | Zhuang, Siwei (Data6... | hw/riscv: Add optional symbol callback ptr to riscv_load_ker... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-25 | Palmer Dabbelt | RISC-V: virt: This is a "sifive,test1" test finisher Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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