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hw/riscv: opentitan: Expose the resetvec as a SoC property
2022-09-26
Alistair
Francis
hw/riscv: opentitan: Expose the
r
esetvec as a S
o
C
property
commit
|
commitdiff
|
tree
2022-09-26
A
li
s
tai
r
Francis
h
w
/riscv:
ope
n
titan: Fi
x
up r
e
setvec
commit
|
commitdiff
|
tree
2022-09-26
Alist
a
ir F
r
an
c
is
tar
g
et/ris
c
v: Set the CPU resetv
e
c directly
commit
|
commitdiff
|
tree
2022-09-26
Andrew
B
urgess
ta
r
get/riscv: remove f
i
xed numbering from GDB
xml feature
.
.
.
commit
|
commitdiff
|
tree
2022-09-26
Andrew Burgess
tar
g
et/riscv: remove
f
flags, frm
,
and fc
s
r f
r
om riscv
.
.
.
commit
|
commitdiff
|
tree
2022-09-26
Weiwei Li
target/riscv:
fi
x
cs
r
check for cy
c
l
e{h
}
,
instret{h
.
.
.
commit
|
commitdiff
|
tree
2022-09-26
Rahul
P
a
th
a
k
target/riscv: Remov
e
s
ideleg and sedeleg
commit
|
commitdiff
|
tree
2022-09-26
Alex Bennée
docs/sy
s
tem: clean up code escape for riscv virt p
l
a
t
fo
r
m
commit
|
commitdiff
|
tree
2022-09-26
Wilfred Mal
l
awa
hw/ssi: ibex_spi: update reg addr
commit
|
commitdiff
|
tree
2022-09-26
W
i
lfred Ma
l
lawa
hw/s
s
i: ibex_spi
:
fixup
t
y
po
s
i
n
ibex
_
spi_h
o
st
commit
|
commitdiff
|
tree
2022-07-03
Anup Patel
target
/
r
i
scv: Updat
e
de
f
au
l
t priori
t
y t
a
ble for local
.
.
.
commit
|
commitdiff
|
tree
2022-07-03
A
n
up Pat
e
l
ta
r
get/ris
c
v: Re
m
ove CSRs that
s
et/cle
a
r an IM
S
IC
i
nt
e
rrup
t
.
.
.
commit
|
commitdiff
|
tree
2022-07-03
Anup Pat
e
l
targe
t
/
ris
c
v: Set mi
n
umum pri
v
sp
e
c v
e
r
s
ion f
o
r
mcountinhibit
commit
|
commitdiff
|
tree
2022-07-03
Alistair Francis
hw
/
riscv: boo
t
: Reduce FDT a
d
dress alignment cons
t
raints
commit
|
commitdiff
|
tree
2022-07-03
An
u
p Patel
target/r
i
s
cv
:
Don't force up
d
a
t
e priv spec version
.
.
.
commit
|
commitdiff
|
tree
2022-07-03
Al
i
st
a
ir
F
rancis
target/ris
c
v
: Ibex: Support
p
riv ver
s
ion 1
.
11
commit
|
commitdiff
|
tree
2022-07-03
Alistair Francis
target/
r
i
scv: Fixup MSECCF
G
m
ini
m
u
m priv chec
k
commit
|
commitdiff
|
tree
2022-07-03
Ati
s
h Patra
t
ar
g
et/riscv
:
Suppor
t
mc
y
cle
/
minst
r
et
wr
i
te oper
a
tion
commit
|
commitdiff
|
tree
2022-07-03
A
t
ish Patra
t
arget/riscv: Add
s
u
p
port fo
r
hpmcounter
s
/
hpmev
e
n
t
s
commit
|
commitdiff
|
tree
2022-07-03
Atish Patra
target/r
i
sc
v
: I
m
plem
e
nt
m
c
ountinhibi
t
CSR
commit
|
commitdiff
|
tree
2022-07-03
Atish Patra
target
/
riscv: pmu: Make number of counters conf
i
gura
b
l
e
commit
|
commitdiff
|
tree
2022-07-03
Atish Patr
a
targe
t
/riscv: pm
u
:
R
ename
t
he c
o
unters
e
x
tension to pm
u
commit
|
commitdiff
|
tree
2022-07-03
Atish Patra
target/riscv: Implement PMU CSR predicate function
.
.
.
commit
|
commitdiff
|
tree
2022-07-03
A
tish P
a
tra
target
/
r
i
scv:
F
i
x
PMU CSR predicate function
commit
|
commitdiff
|
tree
2022-07-03
Nicolas Pitr
e
targe
t
/r
i
scv/pmp: guard aga
i
nst PMP range
s
with a n
e
gative
.
.
.
commit
|
commitdiff
|
tree
2022-07-03
Richard Hender
s
on
target/riscv: Minimize the calls
t
o decode_save
_
opc
commit
|
commitdiff
|
tree
2022-07-03
Richard Henderson
t
a
rg
e
t/riscv: Remove ge
n
era
t
e
_exception
_
mtval
commit
|
commitdiff
|
tree
2022-07-03
Richa
r
d Hend
e
rs
o
n
target/ri
s
cv: Set env->bins in gen_exception_ille
g
al
commit
|
commitdiff
|
tree
2022-07-03
Víct
o
r Colo
m
bo
target/riscv: Re
m
ove cond
i
tion guarding register zero
.
.
.
commit
|
commitdiff
|
tree
2021-10-29
Jose Martins
target/
r
iscv: remove force HS exc
e
ption
commit
|
commitdiff
|
tree
2021-10-29
Jose Mart
i
ns
t
arget/riscv:
fix VS interrupts forwarding to HS
commit
|
commitdiff
|
tree
2021-10-21
R
i
c
h
ard He
n
d
erson
targ
e
t/riscv: Replace Disas
C
on
t
ext
.
w
w
ith D
i
s
a
sC
o
nte
x
t
.
ol
commit
|
commitdiff
|
tree
2021-10-21
Richard Henderson
t
arget
/
riscv: R
e
place is_32
b
it
with get_xl/get_xl
e
n
commit
|
commitdiff
|
tree
2021-10-21
Ric
h
ard Henderson
t
a
r
get/r
i
scv
:
Prope
r
ly ch
e
ck SEW
in
amo_op
commit
|
commitdiff
|
tree
2021-10-21
Ri
c
hard Henderson
t
a
rget/riscv: Use REQUIRE_
6
4BIT in amo_c
h
eck64
commit
|
commitdiff
|
tree
2021-10-21
Richard Henderson
target/
r
iscv
:
A
d
d
MXL/S
X
L/UXL to
T
B_FLAGS
commit
|
commitdiff
|
tree
2021-10-21
Richar
d
Henders
o
n
target/riscv
:
R
e
place
riscv
_
cpu_is_32bi
t
with
r
is
c
v_cpu_mxl
commit
|
commitdiff
|
tree
2021-10-21
R
i
cha
r
d
He
n
der
s
on
tar
g
e
t/riscv: Split misa
.
m
xl and m
i
sa
.
ext
commit
|
commitdiff
|
tree
2021-10-21
Richard Hend
e
rson
t
arget
/
riscv: Create RISCVM
X
L enu
m
er
a
tion
commit
|
commitdiff
|
tree
2021-10-21
R
ichard Henderson
targ
e
t/risc
v
:
M
ove cpu_get
_
tb_cp
u
_
state
o
ut
o
f line
commit
|
commitdiff
|
tree
2021-10-21
A
listair Francis
ta
r
get
/
riscv: O
r
gani
s
e the CPU pro
p
e
r
t
i
e
s
commit
|
commitdiff
|
tree
2021-10-21
Alistair Franci
s
target/ris
c
v: R
e
m
ove some unused macros
commit
|
commitdiff
|
tree
2021-10-21
Fra
n
k Chan
g
t
a
r
get/riscv
:
fix
TB_FLAGS
bits ove
r
lapping bug for
.
.
.
commit
|
commitdiff
|
tree
2021-10-21
Mingwang
Li
h
w
/ri
s
cv:
v
ir
t
: U
s
e machine->ra
m
as
the system
m
emory
commit
|
commitdiff
|
tree
2021-10-21
Philipp Tomsich
target/riscv: Fi
x
orc
.
b imp
l
ementati
o
n
commit
|
commitdiff
|
tree
2021-10-21
Travi
s
Geiselbrecht
t
arget/riscv: li
n
e up all of the registers
i
n the info
.
.
.
commit
|
commitdiff
|
tree
2021-10-21
F
rank Chang
target/ri
s
cv: Pass the same value to oprsz and
m
axs
z
.
.
.
commit
|
commitdiff
|
tree