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2019-06-27	Michael Clark	disas/riscv: Disassemble reserved compressed encodings... Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-06-24	Michael Clark	target/riscv: Implement riscv_cpu_unassigned_access Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Update load reservation comment in do_interrupt Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Convert trap debugging to trace events Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Add support for vectored interrupts Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Change local interrupts from edge to level Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	elf: Add RISC-V PSABI ELF header defines Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Remove unnecessary disassembler constraints Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Allow interrupt controllers to claim interrupts Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-03-19	Michael Clark	RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Michael Clark	RISC-V: Add misa runtime write support Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Michael Clark	RISC-V: Add misa.MAFD checks to translate Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Michael Clark	RISC-V: Add misa to DisasContext Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Michael Clark	RISC-V: Use riscv prefix consistently on cpu helpers Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-02-11	Michael Clark	RISC-V: Implement mstatus.TSR/TW/TVM Signed-off-by: Michael Clark <mjc@sifive.com> Co-authored-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-01-09	Michael Clark	RISC-V: Implement existential predicates for CSRs Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-01-09	Michael Clark	RISC-V: Implement atomic mip/sip CSR updates Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2019-01-08	Michael Clark	RISC-V: Implement modular CSR helper interface Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-12-20	Michael Clark	RISC-V: Enable second UART on sifive_e and sifive_u Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-12-20	Michael Clark	RISC-V: Fix PLIC pending bitfield reads Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-12-20	Michael Clark	RISC-V: Fix CLINT timecmp low 32-bit writes Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-12-20	Michael Clark	RISC-V: Add hartid and \n to interrupt logging Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-10-17	Michael Clark	RISC-V: Don't add NULL bootargs to device-tree Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-10-17	Michael Clark	RISC-V: Add missing free for plic_hart_config Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-10-17	Michael Clark	RISC-V: Update CSR and interrupt definitions Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-10-17	Michael Clark	RISC-V: Move non-ops from op_helper to cpu_helper Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-10-17	Michael Clark	RISC-V: Allow setting and clearing multiple irqs Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-09-04	Michael Clark	RISC-V: Simplify riscv_cpu_local_irqs_pending Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-09-04	Michael Clark	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-09-04	Michael Clark	RISC-V: Improve page table walker spec compliance Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-09-04	Michael Clark	RISC-V: Update address bits to support sv39 and sv48	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Mark ROM read-only after copying in code Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: No traps on writes to misa,minstret,mcycle Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Make mtvec/stvec ignore vectored traps Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Add mcycle/minstret support for -icount auto Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Clear mtval/stval on exceptions without info Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Hardwire satp to 0 for no-mmu case Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Update E and I extension order Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Remove erroneous comment from translate.c Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Remove EM_RISCV ELF_MACHINE indirection Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Make virt header comment title consistent Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Make some header guards more specific Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Fix missing break statement in disassembler Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Include instruction hex in disassembly Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Remove unused class definitions Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Remove identity_translate from load_elf Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Use ROM base address and size from memmap Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Make virt board description match spike Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-05-05	Michael Clark	RISC-V: Replace hardcoded constants with enum values Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-29	Michael Clark	RISC-V: Workaround for critical mstatus.FS bug Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-28	Michael Clark	RISC-V: Fix incorrect disassembly for addiw Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-28	Michael Clark	RISC-V: Convert cpu definition to future model Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-20	Michael Clark	RISC-V: Fix riscv_isa_string memory size bug Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V Build Infrastructure Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive Freedom U Series RISC-V Machine Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive Freedom E Series RISC-V Machine Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive RISC-V PRCI Block Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive RISC-V UART Device Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V VirtIO Machine Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive RISC-V Test Finisher Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V Spike Machines Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive RISC-V PLIC Block Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	SiFive RISC-V CLINT Block Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V HART Array Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V HTIF Console Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	Add symbol table callback interface to load_elf Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V Linux User Emulation Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V Physical Memory Protection Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V TCG Code Generation Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V GDB Stub Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V FPU Support Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V CPU Helpers Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V Disassembler Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V CPU Core Definition Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V ELF Machine Definition Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree
2018-03-06	Michael Clark	RISC-V Maintainers Add Michael Clark, Palmer Dabbelt, Sagar Karandikar... Signed-off-by: Michael Clark <mjc@sifive.com>	commit \| commitdiff \| tree

AR7 emulation for QEMU

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