| commit | bb72692cbdbeeef88f4dd1828c1ad6f92cd57b7e | |
| author | Michael Clark <mjc@sifive.com> | |
| Fri, 2 Mar 2018 12:31:14 +0000 (3 01:31 +1300) | ||
| committer | Michael Clark <mjc@sifive.com> | |
| Tue, 6 Mar 2018 19:30:28 +0000 (7 08:30 +1300) | ||
| tree | b7b17ad6fc655dd1073146b4a43f5c3f6815ad81 | treesnapshot (tar.gz zip) |
| parent | 04331d0b56a0cab2e40a39135a92a15266b37c36 | commitdiff |
SiFive RISC-V UART Device
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stefan O'Rear <sorear2@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stefan O'Rear <sorear2@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
| hw/riscv/sifive_uart.c | [new file with mode: 0644] | blob |
| include/hw/riscv/sifive_uart.h | [new file with mode: 0644] | blob |