| commit | 1d1ee55274860bfcc511d50d83c84394c2685ba8 | |
| author | Michael Clark <mjc@sifive.com> | |
| Mon, 5 Mar 2018 21:17:11 +0000 (6 10:17 +1300) | ||
| committer | Michael Clark <mjc@sifive.com> | |
| Sat, 5 May 2018 22:39:38 +0000 (6 10:39 +1200) | ||
| tree | 5b8815298683e783d0518384359c44fd476be1a1 | treesnapshot (tar.gz zip) |
| parent | 6fce529c4b3ecbff17bbd930f6beaac9a6067114 | commitdiff |
RISC-V: Make mtvec/stvec ignore vectored traps
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fields is to drop writes to unsupported bits.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fields is to drop writes to unsupported bits.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
| target/riscv/op_helper.c | diffblobblamehistory |