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hw/intc: sifive_plic: Cleanup remaining functions
2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup remaining functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the read function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the write function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Add a reset function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Jim Shuhw/dma: sifive_pdma: permit 4/8-byte access size of...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Jim Shuhw/dma: sifive_pdma: support high 32-bit access of...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Nikita Shubintarget/riscv/pmp: fix no pmp illegal intrs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Jessica Clarkehw/riscv: Use load address rather than entry point...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Vineet Guptatarget/riscv: Enable bitmanip Zb[abcs] instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Khem Rajriscv: Set 5.4 as minimum kernel version for riscv32
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: Add ELEN checks for widening...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update opivv_vadc_check() comment
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename vmandnot.mm and vmornot...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vector unit-stride mask...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vsetivli instruction
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal estimate...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal square...
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2021-12-20 Hsiangkai Wangtarget/riscv: gdb: support vector registers for rv64...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: trigger illegal instruction...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: implement vstart CSR
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing floating-point/integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: add "set round to odd" rounding mode...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point/integer...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point/integer type...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: introduce floating-point rounding mode...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point min/max instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove integer extract instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove vmford.vv and vmford.vf
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove widening saturating scaled...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width scaling shift instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point reduction...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width floating-point...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing fixed-point clip instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point slide instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: slide instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: mask-register logical instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point compare instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer comparison instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width saturating add...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening integer multiply-add...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing integer right shift...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer add-with-carry/subtract...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width bit shift instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width averaging add and...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer extension instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: whole register move instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point scalar move instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point move instruction
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer scalar move instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: register gather instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: allow load element with sign...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: element index instruction
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: iota instruction
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set-X-first mask bit instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: find-first-set mask bit instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: count population in mask instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point classify instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point square-root instruction
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: take fractional LMUL into vector...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update vext_max_elems() for...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: load/store whole register instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: fault-only-first unit stride...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: fix address index overflow bug...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: index load and store instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: stride load and store instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: configure instructions
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove amo operations instructions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv:1.0: add translation-time nan-box...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: introduce more imm value modes in translator...
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update check functions
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add VMA and VTA
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add fractional LMUL
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove MLEN calculations
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: check MSTATUS_VS when accessing...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Greentime Hutarget/riscv: rvv-1.0: add vlenb register
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add vcsr register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove rvv related codes from...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add translation-time vector...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: introduce writable misa.v field
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add sstatus VS field
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set mstatus.SD bit if mstatus...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add mstatus VS field
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: Use FIELD_EX32() to extract wd field
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: drop vector 0.7.1 and add 1.0 support
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfhmin cpu property
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2021-12-20 Frank Changtarget/riscv: zfh: implement zfhmin extension
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfh cpu property
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point classify
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision floating-point compare
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision convert and move
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision computational
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2021-12-20 Kito Chengtarget/riscv: zfh: half-precision load and store
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2021-11-22 Philippe Mathieu... hw/misc/sifive_u_otp: Do not reset OTP content on hardware...
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2021-11-22 Thomas Huthhw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device...
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2021-11-17 Richard Hendersonmeson.build: Merge riscv32 and riscv64 cpu family
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2021-11-17 Bin Mengtarget/riscv: machine: Sort the .subsections
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2021-10-29 Chih-Min Chaotarget/riscv: change the api for RVF/RVD fmin/fmax
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AR7 emulation for QEMU